Lines Matching +full:rs485 +full:- +full:rts +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (C) 2010 ST-Ericsson SA
11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
14 * not have an RI input, nor do they have DTR or RTS outputs. If
35 #include <linux/dma-mapping.h>
37 #include <linux/delay.h>
82 /* The size of the array - must be last */
260 unsigned int fifosize; /* vendor-specific */
261 unsigned int fixed_baud; /* vendor-set fixed baud rate */
280 return uap->reg_offset[reg]; in pl011_reg_to_offset()
286 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); in pl011_read()
288 return (uap->port.iotype == UPIO_MEM32) ? in pl011_read()
295 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); in pl011_write()
297 if (uap->port.iotype == UPIO_MEM32) in pl011_write()
323 uap->port.icount.rx++; in pl011_fifo_to_tty()
328 uap->port.icount.brk++; in pl011_fifo_to_tty()
329 if (uart_handle_break(&uap->port)) in pl011_fifo_to_tty()
332 uap->port.icount.parity++; in pl011_fifo_to_tty()
334 uap->port.icount.frame++; in pl011_fifo_to_tty()
336 uap->port.icount.overrun++; in pl011_fifo_to_tty()
338 ch &= uap->port.read_status_mask; in pl011_fifo_to_tty()
348 spin_unlock(&uap->port.lock); in pl011_fifo_to_tty()
349 sysrq = uart_handle_sysrq_char(&uap->port, ch & 255); in pl011_fifo_to_tty()
350 spin_lock(&uap->port.lock); in pl011_fifo_to_tty()
353 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); in pl011_fifo_to_tty()
374 sg->buf = dma_alloc_coherent(chan->device->dev, in pl011_sgbuf_init()
376 if (!sg->buf) in pl011_sgbuf_init()
377 return -ENOMEM; in pl011_sgbuf_init()
379 sg_init_table(&sg->sg, 1); in pl011_sgbuf_init()
380 sg_set_page(&sg->sg, phys_to_page(dma_addr), in pl011_sgbuf_init()
382 sg_dma_address(&sg->sg) = dma_addr; in pl011_sgbuf_init()
383 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE; in pl011_sgbuf_init()
391 if (sg->buf) { in pl011_sgbuf_free()
392 dma_free_coherent(chan->device->dev, in pl011_sgbuf_free()
393 PL011_DMA_BUFFER_SIZE, sg->buf, in pl011_sgbuf_free()
394 sg_dma_address(&sg->sg)); in pl011_sgbuf_free()
401 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); in pl011_dma_probe()
402 struct device *dev = uap->port.dev; in pl011_dma_probe()
404 .dst_addr = uap->port.mapbase + in pl011_dma_probe()
408 .dst_maxburst = uap->fifosize >> 1, in pl011_dma_probe()
414 uap->dma_probed = true; in pl011_dma_probe()
417 if (PTR_ERR(chan) == -EPROBE_DEFER) { in pl011_dma_probe()
418 uap->dma_probed = false; in pl011_dma_probe()
423 if (!plat || !plat->dma_filter) { in pl011_dma_probe()
424 dev_info(uap->port.dev, "no DMA platform data\n"); in pl011_dma_probe()
432 chan = dma_request_channel(mask, plat->dma_filter, in pl011_dma_probe()
433 plat->dma_tx_param); in pl011_dma_probe()
435 dev_err(uap->port.dev, "no TX DMA channel!\n"); in pl011_dma_probe()
441 uap->dmatx.chan = chan; in pl011_dma_probe()
443 dev_info(uap->port.dev, "DMA channel TX %s\n", in pl011_dma_probe()
444 dma_chan_name(uap->dmatx.chan)); in pl011_dma_probe()
449 if (!chan && plat && plat->dma_rx_param) { in pl011_dma_probe()
450 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); in pl011_dma_probe()
453 dev_err(uap->port.dev, "no RX DMA channel!\n"); in pl011_dma_probe()
460 .src_addr = uap->port.mapbase + in pl011_dma_probe()
464 .src_maxburst = uap->fifosize >> 2, in pl011_dma_probe()
478 dev_info(uap->port.dev, in pl011_dma_probe()
479 "RX DMA disabled - no residue processing\n"); in pl011_dma_probe()
484 uap->dmarx.chan = chan; in pl011_dma_probe()
486 uap->dmarx.auto_poll_rate = false; in pl011_dma_probe()
487 if (plat && plat->dma_rx_poll_enable) { in pl011_dma_probe()
489 if (plat->dma_rx_poll_rate) { in pl011_dma_probe()
490 uap->dmarx.auto_poll_rate = false; in pl011_dma_probe()
491 uap->dmarx.poll_rate = plat->dma_rx_poll_rate; in pl011_dma_probe()
498 uap->dmarx.auto_poll_rate = true; in pl011_dma_probe()
499 uap->dmarx.poll_rate = 100; in pl011_dma_probe()
502 if (plat->dma_rx_poll_timeout) in pl011_dma_probe()
503 uap->dmarx.poll_timeout = in pl011_dma_probe()
504 plat->dma_rx_poll_timeout; in pl011_dma_probe()
506 uap->dmarx.poll_timeout = 3000; in pl011_dma_probe()
507 } else if (!plat && dev->of_node) { in pl011_dma_probe()
508 uap->dmarx.auto_poll_rate = of_property_read_bool( in pl011_dma_probe()
509 dev->of_node, "auto-poll"); in pl011_dma_probe()
510 if (uap->dmarx.auto_poll_rate) { in pl011_dma_probe()
513 if (0 == of_property_read_u32(dev->of_node, in pl011_dma_probe()
514 "poll-rate-ms", &x)) in pl011_dma_probe()
515 uap->dmarx.poll_rate = x; in pl011_dma_probe()
517 uap->dmarx.poll_rate = 100; in pl011_dma_probe()
518 if (0 == of_property_read_u32(dev->of_node, in pl011_dma_probe()
519 "poll-timeout-ms", &x)) in pl011_dma_probe()
520 uap->dmarx.poll_timeout = x; in pl011_dma_probe()
522 uap->dmarx.poll_timeout = 3000; in pl011_dma_probe()
525 dev_info(uap->port.dev, "DMA channel RX %s\n", in pl011_dma_probe()
526 dma_chan_name(uap->dmarx.chan)); in pl011_dma_probe()
532 if (uap->dmatx.chan) in pl011_dma_remove()
533 dma_release_channel(uap->dmatx.chan); in pl011_dma_remove()
534 if (uap->dmarx.chan) in pl011_dma_remove()
535 dma_release_channel(uap->dmarx.chan); in pl011_dma_remove()
549 struct pl011_dmatx_data *dmatx = &uap->dmatx; in pl011_dma_tx_callback()
553 spin_lock_irqsave(&uap->port.lock, flags); in pl011_dma_tx_callback()
554 if (uap->dmatx.queued) in pl011_dma_tx_callback()
555 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, in pl011_dma_tx_callback()
558 dmacr = uap->dmacr; in pl011_dma_tx_callback()
559 uap->dmacr = dmacr & ~UART011_TXDMAE; in pl011_dma_tx_callback()
560 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_callback()
564 * some reason (eg, XOFF received, or we want to send an X-char.) in pl011_dma_tx_callback()
567 * and the rest of the driver - if the driver disables TX DMA while in pl011_dma_tx_callback()
571 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || in pl011_dma_tx_callback()
572 uart_circ_empty(&uap->port.state->xmit)) { in pl011_dma_tx_callback()
573 uap->dmatx.queued = false; in pl011_dma_tx_callback()
574 spin_unlock_irqrestore(&uap->port.lock, flags); in pl011_dma_tx_callback()
581 * have data pending to be sent. Re-enable the TX IRQ. in pl011_dma_tx_callback()
585 spin_unlock_irqrestore(&uap->port.lock, flags); in pl011_dma_tx_callback()
598 struct pl011_dmatx_data *dmatx = &uap->dmatx; in pl011_dma_tx_refill()
599 struct dma_chan *chan = dmatx->chan; in pl011_dma_tx_refill()
600 struct dma_device *dma_dev = chan->device; in pl011_dma_tx_refill()
602 struct circ_buf *xmit = &uap->port.state->xmit; in pl011_dma_tx_refill()
612 if (count < (uap->fifosize >> 1)) { in pl011_dma_tx_refill()
613 uap->dmatx.queued = false; in pl011_dma_tx_refill()
621 count -= 1; in pl011_dma_tx_refill()
627 if (xmit->tail < xmit->head) in pl011_dma_tx_refill()
628 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); in pl011_dma_tx_refill()
630 size_t first = UART_XMIT_SIZE - xmit->tail; in pl011_dma_tx_refill()
635 second = count - first; in pl011_dma_tx_refill()
637 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); in pl011_dma_tx_refill()
639 memcpy(&dmatx->buf[first], &xmit->buf[0], second); in pl011_dma_tx_refill()
642 dmatx->sg.length = count; in pl011_dma_tx_refill()
644 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { in pl011_dma_tx_refill()
645 uap->dmatx.queued = false; in pl011_dma_tx_refill()
646 dev_dbg(uap->port.dev, "unable to map TX DMA\n"); in pl011_dma_tx_refill()
647 return -EBUSY; in pl011_dma_tx_refill()
650 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV, in pl011_dma_tx_refill()
653 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); in pl011_dma_tx_refill()
654 uap->dmatx.queued = false; in pl011_dma_tx_refill()
659 dev_dbg(uap->port.dev, "TX DMA busy\n"); in pl011_dma_tx_refill()
660 return -EBUSY; in pl011_dma_tx_refill()
664 desc->callback = pl011_dma_tx_callback; in pl011_dma_tx_refill()
665 desc->callback_param = uap; in pl011_dma_tx_refill()
671 dma_dev->device_issue_pending(chan); in pl011_dma_tx_refill()
673 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_refill()
674 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_refill()
675 uap->dmatx.queued = true; in pl011_dma_tx_refill()
681 uart_xmit_advance(&uap->port, count); in pl011_dma_tx_refill()
684 uart_write_wakeup(&uap->port); in pl011_dma_tx_refill()
690 * We received a transmit interrupt without a pending X-char but with
699 if (!uap->using_tx_dma) in pl011_dma_tx_irq()
704 * TX interrupt, it will be because we've just sent an X-char. in pl011_dma_tx_irq()
707 if (uap->dmatx.queued) { in pl011_dma_tx_irq()
708 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_irq()
709 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_irq()
710 uap->im &= ~UART011_TXIM; in pl011_dma_tx_irq()
711 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_tx_irq()
720 uap->im &= ~UART011_TXIM; in pl011_dma_tx_irq()
721 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_tx_irq()
733 if (uap->dmatx.queued) { in pl011_dma_tx_stop()
734 uap->dmacr &= ~UART011_TXDMAE; in pl011_dma_tx_stop()
735 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_stop()
751 if (!uap->using_tx_dma) in pl011_dma_tx_start()
754 if (!uap->port.x_char) { in pl011_dma_tx_start()
755 /* no X-char, try to push chars out in DMA mode */ in pl011_dma_tx_start()
758 if (!uap->dmatx.queued) { in pl011_dma_tx_start()
760 uap->im &= ~UART011_TXIM; in pl011_dma_tx_start()
761 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_tx_start()
764 } else if (!(uap->dmacr & UART011_TXDMAE)) { in pl011_dma_tx_start()
765 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_start()
766 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_start()
772 * We have an X-char to send. Disable DMA to prevent it loading in pl011_dma_tx_start()
775 dmacr = uap->dmacr; in pl011_dma_tx_start()
776 uap->dmacr &= ~UART011_TXDMAE; in pl011_dma_tx_start()
777 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_start()
783 * loaded the character, we should just re-enable DMA. in pl011_dma_tx_start()
788 pl011_write(uap->port.x_char, uap, REG_DR); in pl011_dma_tx_start()
789 uap->port.icount.tx++; in pl011_dma_tx_start()
790 uap->port.x_char = 0; in pl011_dma_tx_start()
792 /* Success - restore the DMA state */ in pl011_dma_tx_start()
793 uap->dmacr = dmacr; in pl011_dma_tx_start()
804 __releases(&uap->port.lock) in pl011_dma_flush_buffer()
805 __acquires(&uap->port.lock) in pl011_dma_flush_buffer()
810 if (!uap->using_tx_dma) in pl011_dma_flush_buffer()
813 dmaengine_terminate_async(uap->dmatx.chan); in pl011_dma_flush_buffer()
815 if (uap->dmatx.queued) { in pl011_dma_flush_buffer()
816 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, in pl011_dma_flush_buffer()
818 uap->dmatx.queued = false; in pl011_dma_flush_buffer()
819 uap->dmacr &= ~UART011_TXDMAE; in pl011_dma_flush_buffer()
820 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_flush_buffer()
828 struct dma_chan *rxchan = uap->dmarx.chan; in pl011_dma_rx_trigger_dma()
829 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_trigger_dma()
834 return -EIO; in pl011_dma_rx_trigger_dma()
837 sgbuf = uap->dmarx.use_buf_b ? in pl011_dma_rx_trigger_dma()
838 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; in pl011_dma_rx_trigger_dma()
839 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1, in pl011_dma_rx_trigger_dma()
848 uap->dmarx.running = false; in pl011_dma_rx_trigger_dma()
850 return -EBUSY; in pl011_dma_rx_trigger_dma()
854 desc->callback = pl011_dma_rx_callback; in pl011_dma_rx_trigger_dma()
855 desc->callback_param = uap; in pl011_dma_rx_trigger_dma()
856 dmarx->cookie = dmaengine_submit(desc); in pl011_dma_rx_trigger_dma()
859 uap->dmacr |= UART011_RXDMAE; in pl011_dma_rx_trigger_dma()
860 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_rx_trigger_dma()
861 uap->dmarx.running = true; in pl011_dma_rx_trigger_dma()
863 uap->im &= ~UART011_RXIM; in pl011_dma_rx_trigger_dma()
864 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_rx_trigger_dma()
872 * with the port spinlock uap->port.lock held.
878 struct tty_port *port = &uap->port.state->port; in pl011_dma_rx_chars()
880 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; in pl011_dma_rx_chars()
884 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_chars()
887 if (uap->dmarx.poll_rate) { in pl011_dma_rx_chars()
889 dmataken = sgbuf->sg.length - dmarx->last_residue; in pl011_dma_rx_chars()
892 pending -= dmataken; in pl011_dma_rx_chars()
903 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, in pl011_dma_rx_chars()
906 uap->port.icount.rx += dma_count; in pl011_dma_rx_chars()
908 dev_warn(uap->port.dev, in pl011_dma_rx_chars()
913 if (uap->dmarx.poll_rate) in pl011_dma_rx_chars()
914 dmarx->last_residue = sgbuf->sg.length; in pl011_dma_rx_chars()
939 dev_vdbg(uap->port.dev, in pl011_dma_rx_chars()
947 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_irq()
948 struct dma_chan *rxchan = dmarx->chan; in pl011_dma_rx_irq()
949 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? in pl011_dma_rx_irq()
950 &dmarx->sgbuf_b : &dmarx->sgbuf_a; in pl011_dma_rx_irq()
961 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); in pl011_dma_rx_irq()
962 dmastat = rxchan->device->device_tx_status(rxchan, in pl011_dma_rx_irq()
963 dmarx->cookie, &state); in pl011_dma_rx_irq()
965 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); in pl011_dma_rx_irq()
967 /* Disable RX DMA - incoming data will wait in the FIFO */ in pl011_dma_rx_irq()
968 uap->dmacr &= ~UART011_RXDMAE; in pl011_dma_rx_irq()
969 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_rx_irq()
970 uap->dmarx.running = false; in pl011_dma_rx_irq()
972 pending = sgbuf->sg.length - state.residue; in pl011_dma_rx_irq()
974 /* Then we terminate the transfer - we now know our residue */ in pl011_dma_rx_irq()
981 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); in pl011_dma_rx_irq()
983 /* Switch buffer & re-trigger DMA job */ in pl011_dma_rx_irq()
984 dmarx->use_buf_b = !dmarx->use_buf_b; in pl011_dma_rx_irq()
986 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " in pl011_dma_rx_irq()
988 uap->im |= UART011_RXIM; in pl011_dma_rx_irq()
989 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_rx_irq()
996 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_callback()
997 struct dma_chan *rxchan = dmarx->chan; in pl011_dma_rx_callback()
998 bool lastbuf = dmarx->use_buf_b; in pl011_dma_rx_callback()
999 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? in pl011_dma_rx_callback()
1000 &dmarx->sgbuf_b : &dmarx->sgbuf_a; in pl011_dma_rx_callback()
1012 spin_lock_irq(&uap->port.lock); in pl011_dma_rx_callback()
1017 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); in pl011_dma_rx_callback()
1018 pending = sgbuf->sg.length - state.residue; in pl011_dma_rx_callback()
1020 /* Then we terminate the transfer - we now know our residue */ in pl011_dma_rx_callback()
1023 uap->dmarx.running = false; in pl011_dma_rx_callback()
1024 dmarx->use_buf_b = !lastbuf; in pl011_dma_rx_callback()
1028 spin_unlock_irq(&uap->port.lock); in pl011_dma_rx_callback()
1034 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " in pl011_dma_rx_callback()
1036 uap->im |= UART011_RXIM; in pl011_dma_rx_callback()
1037 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_rx_callback()
1048 if (!uap->using_rx_dma) in pl011_dma_rx_stop()
1052 uap->dmacr &= ~UART011_RXDMAE; in pl011_dma_rx_stop()
1053 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_rx_stop()
1064 struct tty_port *port = &uap->port.state->port; in pl011_dma_rx_poll()
1065 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_poll()
1066 struct dma_chan *rxchan = uap->dmarx.chan; in pl011_dma_rx_poll()
1074 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; in pl011_dma_rx_poll()
1075 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); in pl011_dma_rx_poll()
1076 if (likely(state.residue < dmarx->last_residue)) { in pl011_dma_rx_poll()
1077 dmataken = sgbuf->sg.length - dmarx->last_residue; in pl011_dma_rx_poll()
1078 size = dmarx->last_residue - state.residue; in pl011_dma_rx_poll()
1079 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, in pl011_dma_rx_poll()
1082 dmarx->last_residue = state.residue; in pl011_dma_rx_poll()
1083 dmarx->last_jiffies = jiffies; in pl011_dma_rx_poll()
1091 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) in pl011_dma_rx_poll()
1092 > uap->dmarx.poll_timeout) { in pl011_dma_rx_poll()
1094 spin_lock_irqsave(&uap->port.lock, flags); in pl011_dma_rx_poll()
1096 uap->im |= UART011_RXIM; in pl011_dma_rx_poll()
1097 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_rx_poll()
1098 spin_unlock_irqrestore(&uap->port.lock, flags); in pl011_dma_rx_poll()
1100 uap->dmarx.running = false; in pl011_dma_rx_poll()
1102 del_timer(&uap->dmarx.timer); in pl011_dma_rx_poll()
1104 mod_timer(&uap->dmarx.timer, in pl011_dma_rx_poll()
1105 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); in pl011_dma_rx_poll()
1113 if (!uap->dma_probed) in pl011_dma_startup()
1116 if (!uap->dmatx.chan) in pl011_dma_startup()
1119 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); in pl011_dma_startup()
1120 if (!uap->dmatx.buf) { in pl011_dma_startup()
1121 dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); in pl011_dma_startup()
1122 uap->port.fifosize = uap->fifosize; in pl011_dma_startup()
1126 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); in pl011_dma_startup()
1129 uap->port.fifosize = PL011_DMA_BUFFER_SIZE; in pl011_dma_startup()
1130 uap->using_tx_dma = true; in pl011_dma_startup()
1132 if (!uap->dmarx.chan) in pl011_dma_startup()
1136 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, in pl011_dma_startup()
1139 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", in pl011_dma_startup()
1144 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, in pl011_dma_startup()
1147 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", in pl011_dma_startup()
1149 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, in pl011_dma_startup()
1154 uap->using_rx_dma = true; in pl011_dma_startup()
1158 uap->dmacr |= UART011_DMAONERR; in pl011_dma_startup()
1159 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_startup()
1166 if (uap->vendor->dma_threshold) in pl011_dma_startup()
1170 if (uap->using_rx_dma) { in pl011_dma_startup()
1172 dev_dbg(uap->port.dev, "could not trigger initial " in pl011_dma_startup()
1174 if (uap->dmarx.poll_rate) { in pl011_dma_startup()
1175 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0); in pl011_dma_startup()
1176 mod_timer(&uap->dmarx.timer, in pl011_dma_startup()
1178 msecs_to_jiffies(uap->dmarx.poll_rate)); in pl011_dma_startup()
1179 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; in pl011_dma_startup()
1180 uap->dmarx.last_jiffies = jiffies; in pl011_dma_startup()
1187 if (!(uap->using_tx_dma || uap->using_rx_dma)) in pl011_dma_shutdown()
1191 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) in pl011_dma_shutdown()
1194 spin_lock_irq(&uap->port.lock); in pl011_dma_shutdown()
1195 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); in pl011_dma_shutdown()
1196 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_shutdown()
1197 spin_unlock_irq(&uap->port.lock); in pl011_dma_shutdown()
1199 if (uap->using_tx_dma) { in pl011_dma_shutdown()
1201 dmaengine_terminate_all(uap->dmatx.chan); in pl011_dma_shutdown()
1202 if (uap->dmatx.queued) { in pl011_dma_shutdown()
1203 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, in pl011_dma_shutdown()
1205 uap->dmatx.queued = false; in pl011_dma_shutdown()
1208 kfree(uap->dmatx.buf); in pl011_dma_shutdown()
1209 uap->using_tx_dma = false; in pl011_dma_shutdown()
1212 if (uap->using_rx_dma) { in pl011_dma_shutdown()
1213 dmaengine_terminate_all(uap->dmarx.chan); in pl011_dma_shutdown()
1215 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); in pl011_dma_shutdown()
1216 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); in pl011_dma_shutdown()
1217 if (uap->dmarx.poll_rate) in pl011_dma_shutdown()
1218 del_timer_sync(&uap->dmarx.timer); in pl011_dma_shutdown()
1219 uap->using_rx_dma = false; in pl011_dma_shutdown()
1225 return uap->using_rx_dma; in pl011_dma_rx_available()
1230 return uap->using_rx_dma && uap->dmarx.running; in pl011_dma_rx_running()
1271 return -EIO; in pl011_dma_rx_trigger_dma()
1293 const int MAX_TX_DRAIN_ITERS = uap->port.fifosize * 2; in pl011_rs485_tx_stop()
1294 struct uart_port *port = &uap->port; in pl011_rs485_tx_stop()
1301 dev_warn(port->dev, in pl011_rs485_tx_stop()
1306 udelay(uap->rs485_tx_drain_interval); in pl011_rs485_tx_stop()
1310 if (port->rs485.delay_rts_after_send) in pl011_rs485_tx_stop()
1311 mdelay(port->rs485.delay_rts_after_send); in pl011_rs485_tx_stop()
1315 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in pl011_rs485_tx_stop()
1325 uap->rs485_tx_started = false; in pl011_rs485_tx_stop()
1333 uap->im &= ~UART011_TXIM; in pl011_stop_tx()
1334 pl011_write(uap->im, uap, REG_IMSC); in pl011_stop_tx()
1337 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started) in pl011_stop_tx()
1347 uap->im |= UART011_TXIM; in pl011_start_tx_pio()
1348 pl011_write(uap->im, uap, REG_IMSC); in pl011_start_tx_pio()
1366 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| in pl011_stop_rx()
1368 pl011_write(uap->im, uap, REG_IMSC); in pl011_stop_rx()
1377 spin_lock_irqsave(&port->lock, flags); in pl011_throttle_rx()
1379 spin_unlock_irqrestore(&port->lock, flags); in pl011_throttle_rx()
1387 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; in pl011_enable_ms()
1388 pl011_write(uap->im, uap, REG_IMSC); in pl011_enable_ms()
1392 __releases(&uap->port.lock) in pl011_rx_chars()
1393 __acquires(&uap->port.lock) in pl011_rx_chars()
1397 spin_unlock(&uap->port.lock); in pl011_rx_chars()
1398 tty_flip_buffer_push(&uap->port.state->port); in pl011_rx_chars()
1405 dev_dbg(uap->port.dev, "could not trigger RX DMA job " in pl011_rx_chars()
1407 uap->im |= UART011_RXIM; in pl011_rx_chars()
1408 pl011_write(uap->im, uap, REG_IMSC); in pl011_rx_chars()
1412 if (uap->dmarx.poll_rate) { in pl011_rx_chars()
1413 uap->dmarx.last_jiffies = jiffies; in pl011_rx_chars()
1414 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; in pl011_rx_chars()
1415 mod_timer(&uap->dmarx.timer, in pl011_rx_chars()
1417 msecs_to_jiffies(uap->dmarx.poll_rate)); in pl011_rx_chars()
1422 spin_lock(&uap->port.lock); in pl011_rx_chars()
1433 uap->port.icount.tx++; in pl011_tx_char()
1440 struct uart_port *port = &uap->port; in pl011_rs485_tx_start()
1447 /* Disable receiver if half-duplex */ in pl011_rs485_tx_start()
1448 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) in pl011_rs485_tx_start()
1451 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) in pl011_rs485_tx_start()
1458 if (port->rs485.delay_rts_before_send) in pl011_rs485_tx_start()
1459 mdelay(port->rs485.delay_rts_before_send); in pl011_rs485_tx_start()
1461 uap->rs485_tx_started = true; in pl011_rs485_tx_start()
1467 struct circ_buf *xmit = &uap->port.state->xmit; in pl011_tx_chars()
1468 int count = uap->fifosize >> 1; in pl011_tx_chars()
1470 if ((uap->port.rs485.flags & SER_RS485_ENABLED) && in pl011_tx_chars()
1471 !uap->rs485_tx_started) in pl011_tx_chars()
1474 if (uap->port.x_char) { in pl011_tx_chars()
1475 if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) in pl011_tx_chars()
1477 uap->port.x_char = 0; in pl011_tx_chars()
1478 --count; in pl011_tx_chars()
1480 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { in pl011_tx_chars()
1481 pl011_stop_tx(&uap->port); in pl011_tx_chars()
1490 if (likely(from_irq) && count-- == 0) in pl011_tx_chars()
1493 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq)) in pl011_tx_chars()
1496 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in pl011_tx_chars()
1500 uart_write_wakeup(&uap->port); in pl011_tx_chars()
1503 pl011_stop_tx(&uap->port); in pl011_tx_chars()
1515 delta = status ^ uap->old_status; in pl011_modem_status()
1516 uap->old_status = status; in pl011_modem_status()
1522 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); in pl011_modem_status()
1524 if (delta & uap->vendor->fr_dsr) in pl011_modem_status()
1525 uap->port.icount.dsr++; in pl011_modem_status()
1527 if (delta & uap->vendor->fr_cts) in pl011_modem_status()
1528 uart_handle_cts_change(&uap->port, in pl011_modem_status()
1529 status & uap->vendor->fr_cts); in pl011_modem_status()
1531 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); in pl011_modem_status()
1536 if (!uap->vendor->cts_event_workaround) in check_apply_cts_event_workaround()
1543 * WA: introduce 26ns(1 uart clk) delay before W1C; in check_apply_cts_event_workaround()
1544 * single apb access will incur 2 pclk(133.12Mhz) delay, in check_apply_cts_event_workaround()
1558 spin_lock_irqsave(&uap->port.lock, flags); in pl011_int()
1559 status = pl011_read(uap, REG_RIS) & uap->im; in pl011_int()
1580 if (pass_counter-- == 0) in pl011_int()
1583 status = pl011_read(uap, REG_RIS) & uap->im; in pl011_int()
1588 spin_unlock_irqrestore(&uap->port.lock, flags); in pl011_int()
1599 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr; in pl011_tx_empty()
1601 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ? in pl011_tx_empty()
1617 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR); in pl011_get_mctrl()
1618 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS); in pl011_get_mctrl()
1619 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG); in pl011_get_mctrl()
1644 if (port->status & UPSTAT_AUTORTS) { in pl011_set_mctrl()
1645 /* We need to disable auto-RTS if we want to turn RTS off */ in pl011_set_mctrl()
1660 spin_lock_irqsave(&uap->port.lock, flags); in pl011_break_ctl()
1662 if (break_state == -1) in pl011_break_ctl()
1667 spin_unlock_irqrestore(&uap->port.lock, flags); in pl011_break_ctl()
1735 pinctrl_pm_select_default_state(port->dev); in pl011_hwinit()
1740 retval = clk_prepare_enable(uap->clk); in pl011_hwinit()
1744 uap->port.uartclk = clk_get_rate(uap->clk); in pl011_hwinit()
1755 uap->im = pl011_read(uap, REG_IMSC); in pl011_hwinit()
1758 if (dev_get_platdata(uap->port.dev)) { in pl011_hwinit()
1761 plat = dev_get_platdata(uap->port.dev); in pl011_hwinit()
1762 if (plat->init) in pl011_hwinit()
1763 plat->init(); in pl011_hwinit()
1781 * to get this delay write read only register 10 times in pl011_write_lcr_h()
1791 pl011_write(uap->im, uap, REG_IMSC); in pl011_allocate_irq()
1793 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap); in pl011_allocate_irq()
1806 spin_lock_irqsave(&uap->port.lock, flags); in pl011_enable_interrupts()
1817 for (i = 0; i < uap->fifosize * 2; ++i) { in pl011_enable_interrupts()
1824 uap->im = UART011_RTIM; in pl011_enable_interrupts()
1826 uap->im |= UART011_RXIM; in pl011_enable_interrupts()
1827 pl011_write(uap->im, uap, REG_IMSC); in pl011_enable_interrupts()
1828 spin_unlock_irqrestore(&uap->port.lock, flags); in pl011_enable_interrupts()
1836 spin_lock_irqsave(&uap->port.lock, flags); in pl011_unthrottle_rx()
1838 uap->im = UART011_RTIM; in pl011_unthrottle_rx()
1840 uap->im |= UART011_RXIM; in pl011_unthrottle_rx()
1842 pl011_write(uap->im, uap, REG_IMSC); in pl011_unthrottle_rx()
1844 spin_unlock_irqrestore(&uap->port.lock, flags); in pl011_unthrottle_rx()
1862 pl011_write(uap->vendor->ifls, uap, REG_IFLS); in pl011_startup()
1864 spin_lock_irq(&uap->port.lock); in pl011_startup()
1870 if (!(port->rs485.flags & SER_RS485_ENABLED)) in pl011_startup()
1875 spin_unlock_irq(&uap->port.lock); in pl011_startup()
1880 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; in pl011_startup()
1890 clk_disable_unprepare(uap->clk); in pl011_startup()
1909 uap->old_status = 0; in sbsa_uart_startup()
1927 * disable the port. It should not disable RTS and DTR.
1928 * Also RTS and DTR state should be preserved to restore
1935 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); in pl011_disable_uart()
1936 spin_lock_irq(&uap->port.lock); in pl011_disable_uart()
1941 spin_unlock_irq(&uap->port.lock); in pl011_disable_uart()
1953 spin_lock_irq(&uap->port.lock); in pl011_disable_interrupts()
1956 uap->im = 0; in pl011_disable_interrupts()
1957 pl011_write(uap->im, uap, REG_IMSC); in pl011_disable_interrupts()
1960 spin_unlock_irq(&uap->port.lock); in pl011_disable_interrupts()
1972 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started) in pl011_shutdown()
1975 free_irq(uap->port.irq, uap); in pl011_shutdown()
1982 clk_disable_unprepare(uap->clk); in pl011_shutdown()
1984 pinctrl_pm_select_sleep_state(port->dev); in pl011_shutdown()
1986 if (dev_get_platdata(uap->port.dev)) { in pl011_shutdown()
1989 plat = dev_get_platdata(uap->port.dev); in pl011_shutdown()
1990 if (plat->exit) in pl011_shutdown()
1991 plat->exit(); in pl011_shutdown()
1994 if (uap->port.ops->flush_buffer) in pl011_shutdown()
1995 uap->port.ops->flush_buffer(port); in pl011_shutdown()
2005 free_irq(uap->port.irq, uap); in sbsa_uart_shutdown()
2007 if (uap->port.ops->flush_buffer) in sbsa_uart_shutdown()
2008 uap->port.ops->flush_buffer(port); in sbsa_uart_shutdown()
2014 port->read_status_mask = UART011_DR_OE | 255; in pl011_setup_status_masks()
2015 if (termios->c_iflag & INPCK) in pl011_setup_status_masks()
2016 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; in pl011_setup_status_masks()
2017 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in pl011_setup_status_masks()
2018 port->read_status_mask |= UART011_DR_BE; in pl011_setup_status_masks()
2023 port->ignore_status_mask = 0; in pl011_setup_status_masks()
2024 if (termios->c_iflag & IGNPAR) in pl011_setup_status_masks()
2025 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; in pl011_setup_status_masks()
2026 if (termios->c_iflag & IGNBRK) { in pl011_setup_status_masks()
2027 port->ignore_status_mask |= UART011_DR_BE; in pl011_setup_status_masks()
2032 if (termios->c_iflag & IGNPAR) in pl011_setup_status_masks()
2033 port->ignore_status_mask |= UART011_DR_OE; in pl011_setup_status_masks()
2039 if ((termios->c_cflag & CREAD) == 0) in pl011_setup_status_masks()
2040 port->ignore_status_mask |= UART_DUMMY_DR_RX; in pl011_setup_status_masks()
2054 if (uap->vendor->oversampling) in pl011_set_termios()
2063 port->uartclk / clkdiv); in pl011_set_termios()
2068 if (uap->dmarx.auto_poll_rate) in pl011_set_termios()
2069 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); in pl011_set_termios()
2072 if (baud > port->uartclk/16) in pl011_set_termios()
2073 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); in pl011_set_termios()
2075 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); in pl011_set_termios()
2077 switch (termios->c_cflag & CSIZE) { in pl011_set_termios()
2091 if (termios->c_cflag & CSTOPB) in pl011_set_termios()
2093 if (termios->c_cflag & PARENB) { in pl011_set_termios()
2095 if (!(termios->c_cflag & PARODD)) in pl011_set_termios()
2097 if (termios->c_cflag & CMSPAR) in pl011_set_termios()
2100 if (uap->fifosize > 1) in pl011_set_termios()
2103 bits = tty_get_frame_size(termios->c_cflag); in pl011_set_termios()
2105 spin_lock_irqsave(&port->lock, flags); in pl011_set_termios()
2108 * Update the per-port timeout. in pl011_set_termios()
2110 uart_update_timeout(port, termios->c_cflag, baud); in pl011_set_termios()
2117 uap->rs485_tx_drain_interval = DIV_ROUND_UP(bits * 1000 * 1000, baud); in pl011_set_termios()
2121 if (UART_ENABLE_MS(port, termios->c_cflag)) in pl011_set_termios()
2124 if (port->rs485.flags & SER_RS485_ENABLED) in pl011_set_termios()
2125 termios->c_cflag &= ~CRTSCTS; in pl011_set_termios()
2129 if (termios->c_cflag & CRTSCTS) { in pl011_set_termios()
2134 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; in pl011_set_termios()
2137 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); in pl011_set_termios()
2140 if (uap->vendor->oversampling) { in pl011_set_termios()
2141 if (baud > port->uartclk / 16) in pl011_set_termios()
2153 if (uap->vendor->oversampling) { in pl011_set_termios()
2155 quot -= 1; in pl011_set_termios()
2157 quot -= 2; in pl011_set_termios()
2164 * ----------v----------v----------v----------v----- in pl011_set_termios()
2167 * ----------^----------^----------^----------^----- in pl011_set_termios()
2179 spin_unlock_irqrestore(&port->lock, flags); in pl011_set_termios()
2190 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); in sbsa_uart_set_termios()
2193 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); in sbsa_uart_set_termios()
2194 termios->c_cflag &= ~(CMSPAR | CRTSCTS); in sbsa_uart_set_termios()
2195 termios->c_cflag |= CS8 | CLOCAL; in sbsa_uart_set_termios()
2197 spin_lock_irqsave(&port->lock, flags); in sbsa_uart_set_termios()
2198 uart_update_timeout(port, CS8, uap->fixed_baud); in sbsa_uart_set_termios()
2200 spin_unlock_irqrestore(&port->lock, flags); in sbsa_uart_set_termios()
2207 return uap->port.type == PORT_AMBA ? uap->type : NULL; in pl011_type()
2216 port->type = PORT_AMBA; in pl011_config_port()
2225 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) in pl011_verify_port()
2226 ret = -EINVAL; in pl011_verify_port()
2227 if (ser->irq < 0 || ser->irq >= nr_irqs) in pl011_verify_port()
2228 ret = -EINVAL; in pl011_verify_port()
2229 if (ser->baud_base < 9600) in pl011_verify_port()
2230 ret = -EINVAL; in pl011_verify_port()
2231 if (port->mapbase != (unsigned long) ser->iomem_base) in pl011_verify_port()
2232 ret = -EINVAL; in pl011_verify_port()
2237 struct serial_rs485 *rs485) in pl011_rs485_config() argument
2242 if (port->rs485.flags & SER_RS485_ENABLED) in pl011_rs485_config()
2245 /* Make sure auto RTS is disabled */ in pl011_rs485_config()
2246 if (rs485->flags & SER_RS485_ENABLED) { in pl011_rs485_config()
2251 port->status &= ~UPSTAT_AUTORTS; in pl011_rs485_config()
2328 struct uart_amba_port *uap = amba_ports[co->index]; in pl011_console_write()
2333 clk_enable(uap->clk); in pl011_console_write()
2336 if (uap->port.sysrq) in pl011_console_write()
2339 locked = spin_trylock(&uap->port.lock); in pl011_console_write()
2341 spin_lock(&uap->port.lock); in pl011_console_write()
2346 if (!uap->vendor->always_enabled) { in pl011_console_write()
2353 uart_console_write(&uap->port, s, count, pl011_console_putchar); in pl011_console_write()
2360 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr) in pl011_console_write()
2361 & uap->vendor->fr_busy) in pl011_console_write()
2363 if (!uap->vendor->always_enabled) in pl011_console_write()
2367 spin_unlock(&uap->port.lock); in pl011_console_write()
2370 clk_disable(uap->clk); in pl011_console_write()
2397 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); in pl011_console_get_options()
2399 if (uap->vendor->oversampling) { in pl011_console_get_options()
2421 if (co->index >= UART_NR) in pl011_console_setup()
2422 co->index = 0; in pl011_console_setup()
2423 uap = amba_ports[co->index]; in pl011_console_setup()
2425 return -ENODEV; in pl011_console_setup()
2428 pinctrl_pm_select_default_state(uap->port.dev); in pl011_console_setup()
2430 ret = clk_prepare(uap->clk); in pl011_console_setup()
2434 if (dev_get_platdata(uap->port.dev)) { in pl011_console_setup()
2437 plat = dev_get_platdata(uap->port.dev); in pl011_console_setup()
2438 if (plat->init) in pl011_console_setup()
2439 plat->init(); in pl011_console_setup()
2442 uap->port.uartclk = clk_get_rate(uap->clk); in pl011_console_setup()
2444 if (uap->vendor->fixed_options) { in pl011_console_setup()
2445 baud = uap->fixed_baud; in pl011_console_setup()
2454 return uart_set_options(&uap->port, co, baud, parity, bits, flow); in pl011_console_setup()
2458 * pl011_console_match - non-standard console matching
2473 * Returns 0 if console matches; otherwise non-zero to use default matching
2489 return -ENODEV; in pl011_console_match()
2492 return -ENODEV; in pl011_console_match()
2495 return -ENODEV; in pl011_console_match()
2504 port = &amba_ports[i]->port; in pl011_console_match()
2506 if (port->mapbase != addr) in pl011_console_match()
2509 co->index = i; in pl011_console_match()
2510 port->cons = co; in pl011_console_match()
2514 return -ENODEV; in pl011_console_match()
2525 .index = -1,
2533 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) in qdf2400_e44_putc()
2535 writel(c, port->membase + UART01x_DR); in qdf2400_e44_putc()
2536 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE)) in qdf2400_e44_putc()
2542 struct earlycon_device *dev = con->data; in qdf2400_e44_early_write()
2544 uart_console_write(&dev->port, s, n, qdf2400_e44_putc); in qdf2400_e44_early_write()
2549 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) in pl011_putc()
2551 if (port->iotype == UPIO_MEM32) in pl011_putc()
2552 writel(c, port->membase + UART01x_DR); in pl011_putc()
2554 writeb(c, port->membase + UART01x_DR); in pl011_putc()
2555 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) in pl011_putc()
2561 struct earlycon_device *dev = con->data; in pl011_early_write()
2563 uart_console_write(&dev->port, s, n, pl011_putc); in pl011_early_write()
2569 if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE) in pl011_getc()
2572 if (port->iotype == UPIO_MEM32) in pl011_getc()
2573 return readl(port->membase + UART01x_DR); in pl011_getc()
2575 return readb(port->membase + UART01x_DR); in pl011_getc()
2580 struct earlycon_device *dev = con->data; in pl011_early_read()
2584 ch = pl011_getc(&dev->port); in pl011_early_read()
2598 * On non-ACPI systems, earlycon is enabled by specifying
2612 if (!device->port.membase) in pl011_early_console_setup()
2613 return -ENODEV; in pl011_early_console_setup()
2615 device->con->write = pl011_early_write; in pl011_early_console_setup()
2616 device->con->read = pl011_early_read; in pl011_early_console_setup()
2621 OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
2630 * case, the SPCR code will detect the need for the E44 work-around,
2637 if (!device->port.membase) in qdf2400_e44_early_console_setup()
2638 return -ENODEV; in qdf2400_e44_early_console_setup()
2640 device->con->write = qdf2400_e44_early_write; in qdf2400_e44_early_console_setup()
2669 np = dev->of_node; in pl011_probe_dt_alias()
2686 …dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeratio… in pl011_probe_dt_alias()
2716 return -EBUSY; in pl011_find_free_port()
2721 struct uart_port *port = &uap->port; in pl011_get_rs485_mode()
2743 uap->port.dev = dev; in pl011_setup_port()
2744 uap->port.mapbase = mmiobase->start; in pl011_setup_port()
2745 uap->port.membase = base; in pl011_setup_port()
2746 uap->port.fifosize = uap->fifosize; in pl011_setup_port()
2747 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE); in pl011_setup_port()
2748 uap->port.flags = UPF_BOOT_AUTOCONF; in pl011_setup_port()
2749 uap->port.line = index; in pl011_setup_port()
2771 dev_err(uap->port.dev, in pl011_register_port()
2772 "Failed to register AMBA-PL011 driver\n"); in pl011_register_port()
2780 ret = uart_add_one_port(&amba_reg, &uap->port); in pl011_register_port()
2797 struct vendor_data *vendor = id->data; in pl011_probe()
2805 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), in pl011_probe()
2808 return -ENOMEM; in pl011_probe()
2810 uap->clk = devm_clk_get(&dev->dev, NULL); in pl011_probe()
2811 if (IS_ERR(uap->clk)) in pl011_probe()
2812 return PTR_ERR(uap->clk); in pl011_probe()
2814 uap->reg_offset = vendor->reg_offset; in pl011_probe()
2815 uap->vendor = vendor; in pl011_probe()
2816 uap->fifosize = vendor->get_fifosize(dev); in pl011_probe()
2817 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; in pl011_probe()
2818 uap->port.irq = dev->irq[0]; in pl011_probe()
2819 uap->port.ops = &amba_pl011_pops; in pl011_probe()
2820 uap->port.rs485_config = pl011_rs485_config; in pl011_probe()
2821 uap->port.rs485_supported = pl011_rs485_supported; in pl011_probe()
2822 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); in pl011_probe()
2824 if (device_property_read_u32(&dev->dev, "reg-io-width", &val) == 0) { in pl011_probe()
2827 uap->port.iotype = UPIO_MEM; in pl011_probe()
2830 uap->port.iotype = UPIO_MEM32; in pl011_probe()
2833 dev_warn(&dev->dev, "unsupported reg-io-width (%d)\n", in pl011_probe()
2835 return -EINVAL; in pl011_probe()
2839 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); in pl011_probe()
2852 uart_remove_one_port(&amba_reg, &uap->port); in pl011_remove()
2862 return -EINVAL; in pl011_suspend()
2864 return uart_suspend_port(&amba_reg, &uap->port); in pl011_suspend()
2872 return -EINVAL; in pl011_resume()
2874 return uart_resume_port(&amba_reg, &uap->port); in pl011_resume()
2891 if (pdev->dev.of_node) { in sbsa_uart_probe()
2892 struct device_node *np = pdev->dev.of_node; in sbsa_uart_probe()
2894 ret = of_property_read_u32(np, "current-speed", &baudrate); in sbsa_uart_probe()
2905 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), in sbsa_uart_probe()
2908 return -ENOMEM; in sbsa_uart_probe()
2913 uap->port.irq = ret; in sbsa_uart_probe()
2917 dev_info(&pdev->dev, "working around QDF2400 SoC erratum 44\n"); in sbsa_uart_probe()
2918 uap->vendor = &vendor_qdt_qdf2400_e44; in sbsa_uart_probe()
2921 uap->vendor = &vendor_sbsa; in sbsa_uart_probe()
2923 uap->reg_offset = uap->vendor->reg_offset; in sbsa_uart_probe()
2924 uap->fifosize = 32; in sbsa_uart_probe()
2925 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; in sbsa_uart_probe()
2926 uap->port.ops = &sbsa_uart_pops; in sbsa_uart_probe()
2927 uap->fixed_baud = baudrate; in sbsa_uart_probe()
2929 snprintf(uap->type, sizeof(uap->type), "SBSA"); in sbsa_uart_probe()
2933 ret = pl011_setup_port(&pdev->dev, uap, r, portnr); in sbsa_uart_probe()
2946 uart_remove_one_port(&amba_reg, &uap->port); in sbsa_uart_remove()
2952 { .compatible = "arm,sbsa-uart", },
2968 .name = "sbsa-uart",
2994 .name = "uart-pl011",