1 // SPDX-License-Identifier: GPL-2.0
3  *  Probe module for 8250/16550-type MCHP PCI serial ports.
91 	{0,  1,  2, -1}, /* PCI3p012 */
92 	{0,  1,  3, -1}, /* PCI3p013 */
93 	{0,  2,  3, -1}, /* PCI3p023 */
94 	{1,  2,  3, -1}, /* PCI3p123 */
95 	{0,  1, -1, -1}, /* PCI2p01 */
96 	{0,  2, -1, -1}, /* PCI2p02 */
97 	{0,  3, -1, -1}, /* PCI2p03 */
98 	{1,  2, -1, -1}, /* PCI2p12 */
99 	{1,  3, -1, -1}, /* PCI2p13 */
100 	{2,  3, -1, -1}, /* PCI2p23 */
101 	{0, -1, -1, -1}, /* PCI1p0 */
102 	{1, -1, -1, -1}, /* PCI1p1 */
103 	{2, -1, -1, -1}, /* PCI1p2 */
104 	{3, -1, -1, -1}, /* PCI1p3 */
115 	switch (dev->subsystem_device) {  in pci1xxxx_get_num_ports()
154 	*frac = (NSEC_PER_SEC - quot * baud * UART_BIT_SAMPLE_CNT) *  in pci1xxxx_get_divisor()
164 	       port->membase + UART_BAUD_CLK_DIVISOR_REG);  in pci1xxxx_set_divisor()
169 				 struct serial_rs485 *rs485)  in pci1xxxx_rs485_config()  argument
177 	 * pci1xxxx's uart hardware supports only RTS delay after  in pci1xxxx_rs485_config()
180 	if (rs485->flags & SER_RS485_ENABLED) {  in pci1xxxx_rs485_config()
183 		if (!(rs485->flags & SER_RS485_RTS_ON_SEND))  in pci1xxxx_rs485_config()
186 		if (rs485->delay_rts_after_send) {  in pci1xxxx_rs485_config()
187 			clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG);  in pci1xxxx_rs485_config()
192 				rs485->delay_rts_after_send * NSEC_PER_MSEC /  in pci1xxxx_rs485_config()
199 			rs485->delay_rts_after_send =  in pci1xxxx_rs485_config()
204 	writel(mode_cfg, port->membase + ADCL_CFG_REG);  in pci1xxxx_rs485_config()
212 	/* Delay RTS before send is not supported */
218 	struct uart_port *port = &up->port;  in pci1xxxx_port_suspend()
219 	struct tty_port *tport = &port->state->port;  in pci1xxxx_port_suspend()
224 	mutex_lock(&tport->mutex);  in pci1xxxx_port_suspend()
225 	if (port->suspended == 0 && port->dev) {  in pci1xxxx_port_suspend()
226 		wakeup_mask = readb(up->port.membase + UART_WAKE_MASK_REG);  in pci1xxxx_port_suspend()
228 		spin_lock_irqsave(&port->lock, flags);  in pci1xxxx_port_suspend()
229 		port->mctrl &= ~TIOCM_OUT2;  in pci1xxxx_port_suspend()
230 		port->ops->set_mctrl(port, port->mctrl);  in pci1xxxx_port_suspend()
231 		spin_unlock_irqrestore(&port->lock, flags);  in pci1xxxx_port_suspend()
236 	writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG);  in pci1xxxx_port_suspend()
237 	mutex_unlock(&tport->mutex);  in pci1xxxx_port_suspend()
245 	struct uart_port *port = &up->port;  in pci1xxxx_port_resume()
246 	struct tty_port *tport = &port->state->port;  in pci1xxxx_port_resume()
249 	mutex_lock(&tport->mutex);  in pci1xxxx_port_resume()
250 	writeb(UART_BLOCK_SET_ACTIVE, port->membase + UART_ACTV_REG);  in pci1xxxx_port_resume()
251 	writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG);  in pci1xxxx_port_resume()
253 	if (port->suspended == 0) {  in pci1xxxx_port_resume()
254 		spin_lock_irqsave(&port->lock, flags);  in pci1xxxx_port_resume()
255 		port->mctrl |= TIOCM_OUT2;  in pci1xxxx_port_resume()
256 		port->ops->set_mctrl(port, port->mctrl);  in pci1xxxx_port_resume()
257 		spin_unlock_irqrestore(&port->lock, flags);  in pci1xxxx_port_resume()
259 	mutex_unlock(&tport->mutex);  in pci1xxxx_port_resume()
271 	for (i = 0; i < priv->nr; i++) {  in pci1xxxx_suspend()
272 		if (priv->line[i] >= 0) {  in pci1xxxx_suspend()
273 			serial8250_suspend_port(priv->line[i]);  in pci1xxxx_suspend()
274 			wakeup |= pci1xxxx_port_suspend(priv->line[i]);  in pci1xxxx_suspend()
281 		return -ENOMEM;  in pci1xxxx_suspend()
308 		return -ENOMEM;  in pci1xxxx_resume()
315 	for (i = 0; i < priv->nr; i++) {  in pci1xxxx_resume()
316 		if (priv->line[i] >= 0) {  in pci1xxxx_resume()
317 			pci1xxxx_port_resume(priv->line[i]);  in pci1xxxx_resume()
318 			serial8250_resume_port(priv->line[i]);  in pci1xxxx_resume()
330 	port->port.flags |= UPF_FIXED_TYPE | UPF_SKIP_TEST;  in pci1xxxx_setup()
331 	port->port.type = PORT_MCHP16550A;  in pci1xxxx_setup()
332 	port->port.set_termios = serial8250_do_set_termios;  in pci1xxxx_setup()
333 	port->port.get_divisor = pci1xxxx_get_divisor;  in pci1xxxx_setup()
334 	port->port.set_divisor = pci1xxxx_set_divisor;  in pci1xxxx_setup()
335 	port->port.rs485_config = pci1xxxx_rs485_config;  in pci1xxxx_setup()
336 	port->port.rs485_supported = pci1xxxx_rs485_supported;  in pci1xxxx_setup()
342 	writeb(UART_BLOCK_SET_ACTIVE, port->port.membase + UART_ACTV_REG);  in pci1xxxx_setup()
343 	writeb(UART_WAKE_SRCS, port->port.membase + UART_WAKE_REG);  in pci1xxxx_setup()
344 	writeb(UART_WAKE_N_PIN, port->port.membase + UART_WAKE_MASK_REG);  in pci1xxxx_setup()
354 		while (i--) {  in pci1xxxx_get_max_port()
355 			if (logical_to_physical_port_idx[subsys_dev][i] != -1)  in pci1xxxx_get_max_port()
376 	struct device *dev = &pdev->dev;  in pci1xxxx_serial_probe()
394 		return -ENOMEM;  in pci1xxxx_serial_probe()
396 	priv->membase = pci_ioremap_bar(pdev, 0);  in pci1xxxx_serial_probe()
397 	if (!priv->membase)  in pci1xxxx_serial_probe()
398 		return -ENOMEM;  in pci1xxxx_serial_probe()
402 	priv->nr = nr_ports;  in pci1xxxx_serial_probe()
404 	subsys_dev = pdev->subsystem_device;  in pci1xxxx_serial_probe()
409 		pci_iounmap(pdev, priv->membase);  in pci1xxxx_serial_probe()
419 		writeb(UART_PCI_CTRL_SET_MULTIPLE_MSI, priv->membase + UART_PCI_CTRL_REG);  in pci1xxxx_serial_probe()
422 		priv->line[i] = -ENODEV;  in pci1xxxx_serial_probe()
437 		priv->line[i] = serial8250_register_8250_port(&uart);  in pci1xxxx_serial_probe()
438 		if (priv->line[i] < 0) {  in pci1xxxx_serial_probe()
442 				priv->line[i]);  in pci1xxxx_serial_probe()
456 	for (i = 0; i < priv->nr; i++) {  in pci1xxxx_serial_remove()
457 		if (priv->line[i] >= 0)  in pci1xxxx_serial_remove()
458 			serial8250_unregister_port(priv->line[i]);  in pci1xxxx_serial_remove()
462 	pci_iounmap(dev, priv->membase);  in pci1xxxx_serial_remove()