75 	u32 addr = 0;  in get_cfgspace_addr()
82 	if (bus == 0) {  in get_cfgspace_addr()
83 		/* Type 0 transaction */  in get_cfgspace_addr()
131 		val = 0xffffffff;  in ssb_extpci_read_config()
149 	err = 0;  in ssb_extpci_read_config()
162 	u32 addr, val = 0;  in ssb_extpci_write_config()
177 		val = 0xffffffff;  in ssb_extpci_write_config()
184 		val &= ~(0xFF << (8 * (off & 3)));  in ssb_extpci_write_config()
189 		val &= ~(0xFFFF << (8 * (off & 3)));  in ssb_extpci_write_config()
198 	err = 0;  in ssb_extpci_write_config()
247 	.start	= 0x100,
248 	.end	= 0x7FF,
274 	return 0;  in ssb_pcicore_plat_dev_init()
286 	if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)  in ssb_pcicore_fixup_pcibridge()
293 	if (pcibios_enable_device(dev, ~0) < 0) {  in ssb_pcicore_fixup_pcibridge()
348 		pcicore_write16(pc, SSB_PCICORE_SPROM(0),  in ssb_pcicore_init_hostmode()
349 				pcicore_read16(pc, SSB_PCICORE_SPROM(0))  in ssb_pcicore_init_hostmode()
350 				| 0x0400);  in ssb_pcicore_init_hostmode()
365 	 * GPIO reset) was causing reboots on WRT300N v1.0 (BCM4704).  in ssb_pcicore_init_hostmode()
375 	ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2);  in ssb_pcicore_init_hostmode()
377 	val = 0;  in ssb_pcicore_init_hostmode()
378 	ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2);  in ssb_pcicore_init_hostmode()
388 	ssb_pcicore_controller.io_map_base = (unsigned long)ioremap(SSB_PCI_MEM, 0x04000000);  in ssb_pcicore_init_hostmode()
403 	chipid_top = (bus->chip_id & 0xFF00);  in pcicore_is_in_hostmode()
404 	if (chipid_top != 0x4700 &&  in pcicore_is_in_hostmode()
405 	    chipid_top != 0x5300)  in pcicore_is_in_hostmode()
406 		return 0;  in pcicore_is_in_hostmode()
409 		return 0;  in pcicore_is_in_hostmode()
414 	if (bus->chip_id == 0x4712) {  in pcicore_is_in_hostmode()
416 			return 0;  in pcicore_is_in_hostmode()
418 			return 0;  in pcicore_is_in_hostmode()
420 	if (bus->chip_id == 0x5350)  in pcicore_is_in_hostmode()
421 		return 0;  in pcicore_is_in_hostmode()
433 	u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));  in ssb_pcicore_fix_sprom_core_index()
434 	if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {  in ssb_pcicore_fix_sprom_core_index()
435 		tmp &= ~0xF000;  in ssb_pcicore_fix_sprom_core_index()
437 		pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);  in ssb_pcicore_fix_sprom_core_index()
443 	return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;  in ssb_pcicore_polarity_workaround()
448 	const u8 serdes_pll_device = 0x1D;  in ssb_pcicore_serdes_workaround()
449 	const u8 serdes_rx_device = 0x1F;  in ssb_pcicore_serdes_workaround()
455 	if (tmp & 0x4000)  in ssb_pcicore_serdes_workaround()
456 		ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);  in ssb_pcicore_serdes_workaround()
490 	if (rev == 0 || rev == 1) {  in ssb_pcicore_pcie_setup_workarounds()
492 		tmp = ssb_pcie_read(pc, 0x4);  in ssb_pcicore_pcie_setup_workarounds()
493 		tmp |= 0x8;  in ssb_pcicore_pcie_setup_workarounds()
494 		ssb_pcie_write(pc, 0x4, tmp);  in ssb_pcicore_pcie_setup_workarounds()
498 		tmp = ssb_pcie_read(pc, 0x100);  in ssb_pcicore_pcie_setup_workarounds()
499 		tmp |= 0x40;  in ssb_pcicore_pcie_setup_workarounds()
500 		ssb_pcie_write(pc, 0x100, tmp);  in ssb_pcicore_pcie_setup_workarounds()
503 	if (rev == 0) {  in ssb_pcicore_pcie_setup_workarounds()
504 		const u8 serdes_rx_device = 0x1F;  in ssb_pcicore_pcie_setup_workarounds()
507 					2 /* Timer */, 0x8128);  in ssb_pcicore_pcie_setup_workarounds()
509 					6 /* CDR */, 0x0100);  in ssb_pcicore_pcie_setup_workarounds()
511 					7 /* CDR BW */, 0x1466);  in ssb_pcicore_pcie_setup_workarounds()
523 		if (!(tmp & 0x8000))  in ssb_pcicore_pcie_setup_workarounds()
525 					tmp | 0x8000);  in ssb_pcicore_pcie_setup_workarounds()
542 	ssb_write32(pdev, SSB_INTVEC, 0);  in ssb_pcicore_init_clientmode()
559 		ssb_device_enable(dev, 0);  in ssb_pcicore_init()
572 	pcicore_write32(pc, 0x130, address);  in ssb_pcie_read()
573 	return pcicore_read32(pc, 0x134);  in ssb_pcie_read()
578 	pcicore_write32(pc, 0x130, address);  in ssb_pcie_write()
579 	pcicore_write32(pc, 0x134, data);  in ssb_pcie_write()
584 	const u16 mdio_control = 0x128;  in ssb_pcie_mdio_set_phy()
585 	const u16 mdio_data = 0x12C;  in ssb_pcie_mdio_set_phy()
592 	v |= (0x1F << 18);  in ssb_pcie_mdio_set_phy()
597 	for (i = 0; i < 200; i++) {  in ssb_pcie_mdio_set_phy()
599 		if (v & 0x100 /* Trans complete */)  in ssb_pcie_mdio_set_phy()
607 	const u16 mdio_control = 0x128;  in ssb_pcie_mdio_read()
608 	const u16 mdio_data = 0x12C;  in ssb_pcie_mdio_read()
610 	u16 ret = 0;  in ssb_pcie_mdio_read()
614 	v = 0x80; /* Enable Preamble Sequence */  in ssb_pcie_mdio_read()
615 	v |= 0x2; /* MDIO Clock Divisor */  in ssb_pcie_mdio_read()
632 	for (i = 0; i < max_retries; i++) {  in ssb_pcie_mdio_read()
634 		if (v & 0x100 /* Trans complete */) {  in ssb_pcie_mdio_read()
641 	pcicore_write32(pc, mdio_control, 0);  in ssb_pcie_mdio_read()
648 	const u16 mdio_control = 0x128;  in ssb_pcie_mdio_write()
649 	const u16 mdio_data = 0x12C;  in ssb_pcie_mdio_write()
654 	v = 0x80; /* Enable Preamble Sequence */  in ssb_pcie_mdio_write()
655 	v |= 0x2; /* MDIO Clock Divisor */  in ssb_pcie_mdio_write()
673 	for (i = 0; i < max_retries; i++) {  in ssb_pcie_mdio_write()
675 		if (v & 0x100 /* Trans complete */)  in ssb_pcie_mdio_write()
679 	pcicore_write32(pc, mdio_control, 0);  in ssb_pcie_mdio_write()
687 	int err = 0;  in ssb_pcicore_dev_irqvecs_enable()