Lines Matching refs:STM32H7_SPI_CR1
78 #define STM32H7_SPI_CR1 0x00 macro
346 .en = { STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE },
387 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); in stm32h7_spi_get_fifo_size()
392 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); in stm32h7_spi_get_fifo_size()
709 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1); in stm32h7_spi_disable()
725 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); in stm32h7_spi_disable()
1192 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); in stm32h7_spi_transfer_one_irq()
1240 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); in stm32h7_spi_transfer_one_dma_start()
1474 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR); in stm32h7_spi_set_mode()
1477 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR); in stm32h7_spi_set_mode()
1739 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, cr1); in stm32h7_spi_config()