Lines Matching refs:clk_freq
1737 ssp_clock_params * clk_freq) in calculate_effective_freq() argument
1801 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); in calculate_effective_freq()
1802 clk_freq->scr = (u8) (best_scr & 0xFF); in calculate_effective_freq()
1807 clk_freq->cpsdvsr, clk_freq->scr); in calculate_effective_freq()
1845 struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0}; in pl022_setup() local
1904 if ((0 == chip_info->clk_freq.cpsdvsr) in pl022_setup()
1905 && (0 == chip_info->clk_freq.scr)) { in pl022_setup()
1908 &clk_freq); in pl022_setup()
1912 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); in pl022_setup()
1913 if ((clk_freq.cpsdvsr % 2) != 0) in pl022_setup()
1914 clk_freq.cpsdvsr = in pl022_setup()
1915 clk_freq.cpsdvsr - 1; in pl022_setup()
1917 if ((clk_freq.cpsdvsr < CPSDVR_MIN) in pl022_setup()
1918 || (clk_freq.cpsdvsr > CPSDVR_MAX)) { in pl022_setup()
1983 chip->cpsr = clk_freq.cpsdvsr; in pl022_setup()
2040 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); in pl022_setup()