Lines Matching refs:SPICC_CONREG
45 #define SPICC_CONREG 0x08 macro
284 spicc->base + SPICC_CONREG); in meson_spicc_setup_burst()
312 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); in meson_spicc_irq()
330 readl_relaxed(spicc->base + SPICC_CONREG)); in meson_spicc_auto_io_delay()
366 conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG); in meson_spicc_setup_xfer()
375 writel_relaxed(conf, spicc->base + SPICC_CONREG); in meson_spicc_setup_xfer()
446 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); in meson_spicc_transfer_one()
462 u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK; in meson_spicc_prepare_message()
512 writel_relaxed(conf, spicc->base + SPICC_CONREG); in meson_spicc_prepare_message()
525 u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK; in meson_spicc_unprepare_transfer()
533 writel_relaxed(conf, spicc->base + SPICC_CONREG); in meson_spicc_unprepare_transfer()
676 spicc->pow2_div.reg = spicc->base + SPICC_CONREG; in meson_spicc_pow2_clk_init()
805 spicc->base + SPICC_CONREG); in meson_spicc_probe()
917 writel(0, spicc->base + SPICC_CONREG); in meson_spicc_remove()