179 	int (*exec_op)(struct intel_spi *ispi,
189 static void intel_spi_dump_regs(struct intel_spi *ispi)  in intel_spi_dump_regs()  argument
194 	dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG));  in intel_spi_dump_regs()
196 	value = readl(ispi->base + HSFSTS_CTL);  in intel_spi_dump_regs()
197 	dev_dbg(ispi->dev, "HSFSTS_CTL=0x%08x\n", value);  in intel_spi_dump_regs()
199 		dev_dbg(ispi->dev, "-> Locked\n");  in intel_spi_dump_regs()
201 	dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR));  in intel_spi_dump_regs()
202 	dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK));  in intel_spi_dump_regs()
205 		dev_dbg(ispi->dev, "FDATA(%d)=0x%08x\n",  in intel_spi_dump_regs()
206 			i, readl(ispi->base + FDATA(i)));  in intel_spi_dump_regs()
208 	dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC));  in intel_spi_dump_regs()
210 	for (i = 0; i < ispi->nregions; i++)  in intel_spi_dump_regs()
211 		dev_dbg(ispi->dev, "FREG(%d)=0x%08x\n", i,  in intel_spi_dump_regs()
212 			readl(ispi->base + FREG(i)));  in intel_spi_dump_regs()
213 	for (i = 0; i < ispi->pr_num; i++)  in intel_spi_dump_regs()
214 		dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i,  in intel_spi_dump_regs()
215 			readl(ispi->pregs + PR(i)));  in intel_spi_dump_regs()
217 	if (ispi->sregs) {  in intel_spi_dump_regs()
218 		value = readl(ispi->sregs + SSFSTS_CTL);  in intel_spi_dump_regs()
219 		dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value);  in intel_spi_dump_regs()
220 		dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n",  in intel_spi_dump_regs()
221 			readl(ispi->sregs + PREOP_OPTYPE));  in intel_spi_dump_regs()
222 		dev_dbg(ispi->dev, "OPMENU0=0x%08x\n",  in intel_spi_dump_regs()
223 			readl(ispi->sregs + OPMENU0));  in intel_spi_dump_regs()
224 		dev_dbg(ispi->dev, "OPMENU1=0x%08x\n",  in intel_spi_dump_regs()
225 			readl(ispi->sregs + OPMENU1));  in intel_spi_dump_regs()
228 	dev_dbg(ispi->dev, "LVSCC=0x%08x\n", readl(ispi->base + LVSCC));  in intel_spi_dump_regs()
229 	dev_dbg(ispi->dev, "UVSCC=0x%08x\n", readl(ispi->base + UVSCC));  in intel_spi_dump_regs()
231 	dev_dbg(ispi->dev, "Protected regions:\n");  in intel_spi_dump_regs()
232 	for (i = 0; i < ispi->pr_num; i++) {  in intel_spi_dump_regs()
235 		value = readl(ispi->pregs + PR(i));  in intel_spi_dump_regs()
242 		dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x [%c%c]\n",  in intel_spi_dump_regs()
247 	dev_dbg(ispi->dev, "Flash regions:\n");  in intel_spi_dump_regs()
248 	for (i = 0; i < ispi->nregions; i++) {  in intel_spi_dump_regs()
251 		region = readl(ispi->base + FREG(i));  in intel_spi_dump_regs()
256 			dev_dbg(ispi->dev, " %02d disabled\n", i);  in intel_spi_dump_regs()
258 			dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x\n",  in intel_spi_dump_regs()
262 	dev_dbg(ispi->dev, "Using %cW sequencer for register access\n",  in intel_spi_dump_regs()
263 		ispi->swseq_reg ? 'S' : 'H');  in intel_spi_dump_regs()
264 	dev_dbg(ispi->dev, "Using %cW sequencer for erase operation\n",  in intel_spi_dump_regs()
265 		ispi->swseq_erase ? 'S' : 'H');  in intel_spi_dump_regs()
269 static int intel_spi_read_block(struct intel_spi *ispi, void *buf, size_t size)  in intel_spi_read_block()  argument
279 		memcpy_fromio(buf, ispi->base + FDATA(i), bytes);  in intel_spi_read_block()
289 static int intel_spi_write_block(struct intel_spi *ispi, const void *buf,  in intel_spi_write_block()  argument
300 		memcpy_toio(ispi->base + FDATA(i), buf, bytes);  in intel_spi_write_block()
309 static int intel_spi_wait_hw_busy(struct intel_spi *ispi)  in intel_spi_wait_hw_busy()  argument
313 	return readl_poll_timeout(ispi->base + HSFSTS_CTL, val,  in intel_spi_wait_hw_busy()
318 static int intel_spi_wait_sw_busy(struct intel_spi *ispi)  in intel_spi_wait_sw_busy()  argument
322 	return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val,  in intel_spi_wait_sw_busy()
327 static bool intel_spi_set_writeable(struct intel_spi *ispi)  in intel_spi_set_writeable()  argument
329 	if (!ispi->info->set_writeable)  in intel_spi_set_writeable()
332 	return ispi->info->set_writeable(ispi->base, ispi->info->data);  in intel_spi_set_writeable()
335 static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode, int optype)  in intel_spi_opcode_index()  argument
340 	if (ispi->locked) {  in intel_spi_opcode_index()
341 		for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++)  in intel_spi_opcode_index()
342 			if (ispi->opcodes[i] == opcode)  in intel_spi_opcode_index()
349 	writel(opcode, ispi->sregs + OPMENU0);  in intel_spi_opcode_index()
350 	preop = readw(ispi->sregs + PREOP_OPTYPE);  in intel_spi_opcode_index()
351 	writel(optype << 16 | preop, ispi->sregs + PREOP_OPTYPE);  in intel_spi_opcode_index()
356 static int intel_spi_hw_cycle(struct intel_spi *ispi,  in intel_spi_hw_cycle()  argument
365 	val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_hw_cycle()
371 	writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_hw_cycle()
373 	ret = intel_spi_wait_hw_busy(ispi);  in intel_spi_hw_cycle()
377 	status = readl(ispi->base + HSFSTS_CTL);  in intel_spi_hw_cycle()
386 static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, size_t len,  in intel_spi_sw_cycle()  argument
393 	ret = intel_spi_opcode_index(ispi, opcode, optype);  in intel_spi_sw_cycle()
401 	atomic_preopcode = ispi->atomic_preopcode;  in intel_spi_sw_cycle()
402 	ispi->atomic_preopcode = 0;  in intel_spi_sw_cycle()
417 			preop = readw(ispi->sregs + PREOP_OPTYPE);  in intel_spi_sw_cycle()
433 	writel(val, ispi->sregs + SSFSTS_CTL);  in intel_spi_sw_cycle()
435 	ret = intel_spi_wait_sw_busy(ispi);  in intel_spi_sw_cycle()
439 	status = readl(ispi->sregs + SSFSTS_CTL);  in intel_spi_sw_cycle()
448 static u32 intel_spi_chip_addr(const struct intel_spi *ispi,  in intel_spi_chip_addr()  argument
454 	return (spi_get_chipselect(mem->spi, 0) == 1) ? ispi->chip0_size : 0;  in intel_spi_chip_addr()
457 static int intel_spi_read_reg(struct intel_spi *ispi, const struct spi_mem *mem,  in intel_spi_read_reg()  argument
461 	u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;  in intel_spi_read_reg()
466 	writel(addr, ispi->base + FADDR);  in intel_spi_read_reg()
468 	if (ispi->swseq_reg)  in intel_spi_read_reg()
469 		ret = intel_spi_sw_cycle(ispi, opcode, nbytes,  in intel_spi_read_reg()
472 		ret = intel_spi_hw_cycle(ispi, iop, nbytes);  in intel_spi_read_reg()
477 	return intel_spi_read_block(ispi, op->data.buf.in, nbytes);  in intel_spi_read_reg()
480 static int intel_spi_write_reg(struct intel_spi *ispi, const struct spi_mem *mem,  in intel_spi_write_reg()  argument
484 	u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;  in intel_spi_write_reg()
501 		if (!ispi->swseq_reg)  in intel_spi_write_reg()
504 		preop = readw(ispi->sregs + PREOP_OPTYPE);  in intel_spi_write_reg()
506 			if (ispi->locked)  in intel_spi_write_reg()
508 			writel(opcode, ispi->sregs + PREOP_OPTYPE);  in intel_spi_write_reg()
515 		ispi->atomic_preopcode = opcode;  in intel_spi_write_reg()
528 	writel(addr, ispi->base + FADDR);  in intel_spi_write_reg()
531 	ret = intel_spi_write_block(ispi, op->data.buf.out, nbytes);  in intel_spi_write_reg()
535 	if (ispi->swseq_reg)  in intel_spi_write_reg()
536 		return intel_spi_sw_cycle(ispi, opcode, nbytes,  in intel_spi_write_reg()
538 	return intel_spi_hw_cycle(ispi, iop, nbytes);  in intel_spi_write_reg()
541 static int intel_spi_read(struct intel_spi *ispi, const struct spi_mem *mem,  in intel_spi_read()  argument
545 	u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;  in intel_spi_read()
555 	if (WARN_ON_ONCE(ispi->atomic_preopcode))  in intel_spi_read()
556 		ispi->atomic_preopcode = 0;  in intel_spi_read()
565 		writel(addr, ispi->base + FADDR);  in intel_spi_read()
567 		val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_read()
573 		writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_read()
575 		ret = intel_spi_wait_hw_busy(ispi);  in intel_spi_read()
579 		status = readl(ispi->base + HSFSTS_CTL);  in intel_spi_read()
586 			dev_err(ispi->dev, "read error: %x: %#x\n", addr, status);  in intel_spi_read()
590 		ret = intel_spi_read_block(ispi, read_buf, block_size);  in intel_spi_read()
602 static int intel_spi_write(struct intel_spi *ispi, const struct spi_mem *mem,  in intel_spi_write()  argument
606 	u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;  in intel_spi_write()
613 	ispi->atomic_preopcode = 0;  in intel_spi_write()
622 		writel(addr, ispi->base + FADDR);  in intel_spi_write()
624 		val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_write()
630 		ret = intel_spi_write_block(ispi, write_buf, block_size);  in intel_spi_write()
632 			dev_err(ispi->dev, "failed to write block\n");  in intel_spi_write()
638 		writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_write()
640 		ret = intel_spi_wait_hw_busy(ispi);  in intel_spi_write()
642 			dev_err(ispi->dev, "timeout\n");  in intel_spi_write()
646 		status = readl(ispi->base + HSFSTS_CTL);  in intel_spi_write()
653 			dev_err(ispi->dev, "write error: %x: %#x\n", addr, status);  in intel_spi_write()
665 static int intel_spi_erase(struct intel_spi *ispi, const struct spi_mem *mem,  in intel_spi_erase()  argument
669 	u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;  in intel_spi_erase()
674 	writel(addr, ispi->base + FADDR);  in intel_spi_erase()
676 	if (ispi->swseq_erase)  in intel_spi_erase()
677 		return intel_spi_sw_cycle(ispi, opcode, 0,  in intel_spi_erase()
681 	ispi->atomic_preopcode = 0;  in intel_spi_erase()
683 	val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_erase()
688 	writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_erase()
690 	ret = intel_spi_wait_hw_busy(ispi);  in intel_spi_erase()
694 	status = readl(ispi->base + HSFSTS_CTL);  in intel_spi_erase()
735 intel_spi_match_mem_op(struct intel_spi *ispi, const struct spi_mem_op *op)  in intel_spi_match_mem_op()  argument
739 	for (iop = ispi->mem_ops; iop->mem_op.cmd.opcode; iop++) {  in intel_spi_match_mem_op()
750 	struct intel_spi *ispi = spi_controller_get_devdata(mem->spi->controller);  in intel_spi_supports_mem_op()  local
753 	iop = intel_spi_match_mem_op(ispi, op);  in intel_spi_supports_mem_op()
755 		dev_dbg(ispi->dev, "%#x not supported\n", op->cmd.opcode);  in intel_spi_supports_mem_op()
763 	if (ispi->swseq_reg && ispi->locked) {  in intel_spi_supports_mem_op()
767 		for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++) {  in intel_spi_supports_mem_op()
768 			if (ispi->opcodes[i] == op->cmd.opcode)  in intel_spi_supports_mem_op()
772 		dev_dbg(ispi->dev, "%#x not supported\n", op->cmd.opcode);  in intel_spi_supports_mem_op()
781 	struct intel_spi *ispi = spi_controller_get_devdata(mem->spi->controller);  in intel_spi_exec_mem_op()  local
784 	iop = intel_spi_match_mem_op(ispi, op);  in intel_spi_exec_mem_op()
788 	return iop->exec_op(ispi, mem, iop, op);  in intel_spi_exec_mem_op()
793 	const struct intel_spi *ispi = spi_controller_get_devdata(mem->spi->controller);  in intel_spi_get_name()  local
799 	return dev_name(ispi->dev);  in intel_spi_get_name()
804 	struct intel_spi *ispi = spi_controller_get_devdata(desc->mem->spi->controller);  in intel_spi_dirmap_create()  local
807 	iop = intel_spi_match_mem_op(ispi, &desc->info.op_tmpl);  in intel_spi_dirmap_create()
818 	struct intel_spi *ispi = spi_controller_get_devdata(desc->mem->spi->controller);  in intel_spi_dirmap_read()  local
828 	ret = iop->exec_op(ispi, desc->mem, iop, &op);  in intel_spi_dirmap_read()
835 	struct intel_spi *ispi = spi_controller_get_devdata(desc->mem->spi->controller);  in intel_spi_dirmap_write()  local
844 	ret = iop->exec_op(ispi, desc->mem, iop, &op);  in intel_spi_dirmap_write()
1069 static int intel_spi_init(struct intel_spi *ispi)  in intel_spi_init()  argument
1075 	switch (ispi->info->type) {  in intel_spi_init()
1077 		ispi->sregs = ispi->base + BYT_SSFSTS_CTL;  in intel_spi_init()
1078 		ispi->pregs = ispi->base + BYT_PR;  in intel_spi_init()
1079 		ispi->nregions = BYT_FREG_NUM;  in intel_spi_init()
1080 		ispi->pr_num = BYT_PR_NUM;  in intel_spi_init()
1081 		ispi->swseq_reg = true;  in intel_spi_init()
1085 		ispi->sregs = ispi->base + LPT_SSFSTS_CTL;  in intel_spi_init()
1086 		ispi->pregs = ispi->base + LPT_PR;  in intel_spi_init()
1087 		ispi->nregions = LPT_FREG_NUM;  in intel_spi_init()
1088 		ispi->pr_num = LPT_PR_NUM;  in intel_spi_init()
1089 		ispi->swseq_reg = true;  in intel_spi_init()
1093 		ispi->sregs = ispi->base + BXT_SSFSTS_CTL;  in intel_spi_init()
1094 		ispi->pregs = ispi->base + BXT_PR;  in intel_spi_init()
1095 		ispi->nregions = BXT_FREG_NUM;  in intel_spi_init()
1096 		ispi->pr_num = BXT_PR_NUM;  in intel_spi_init()
1101 		ispi->sregs = NULL;  in intel_spi_init()
1102 		ispi->pregs = ispi->base + CNL_PR;  in intel_spi_init()
1103 		ispi->nregions = CNL_FREG_NUM;  in intel_spi_init()
1104 		ispi->pr_num = CNL_PR_NUM;  in intel_spi_init()
1113 	if (writeable && !intel_spi_set_writeable(ispi)) {  in intel_spi_init()
1114 		dev_warn(ispi->dev, "can't disable chip write protection\n");  in intel_spi_init()
1119 	val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_init()
1121 	writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_init()
1131 	lvscc = readl(ispi->base + LVSCC);  in intel_spi_init()
1132 	uvscc = readl(ispi->base + UVSCC);  in intel_spi_init()
1134 		ispi->swseq_erase = true;  in intel_spi_init()
1136 	if (ispi->info->type == INTEL_SPI_BXT && !ispi->swseq_erase)  in intel_spi_init()
1141 	if (!ispi->sregs && (ispi->swseq_reg || ispi->swseq_erase)) {  in intel_spi_init()
1142 		dev_err(ispi->dev, "software sequencer not supported, but required\n");  in intel_spi_init()
1151 	if (ispi->swseq_reg) {  in intel_spi_init()
1153 		val = readl(ispi->sregs + SSFSTS_CTL);  in intel_spi_init()
1155 		writel(val, ispi->sregs + SSFSTS_CTL);  in intel_spi_init()
1159 	val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_init()
1160 	ispi->locked = !!(val & HSFSTS_CTL_FLOCKDN);  in intel_spi_init()
1162 	if (ispi->locked && ispi->sregs) {  in intel_spi_init()
1168 		opmenu0 = readl(ispi->sregs + OPMENU0);  in intel_spi_init()
1169 		opmenu1 = readl(ispi->sregs + OPMENU1);  in intel_spi_init()
1172 			for (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) {  in intel_spi_init()
1173 				ispi->opcodes[i] = opmenu0 >> i * 8;  in intel_spi_init()
1174 				ispi->opcodes[i + 4] = opmenu1 >> i * 8;  in intel_spi_init()
1180 		dev_dbg(ispi->dev, "Using erase_64k memory operations");  in intel_spi_init()
1181 		ispi->mem_ops = erase_64k_mem_ops;  in intel_spi_init()
1183 		dev_dbg(ispi->dev, "Using generic memory operations");  in intel_spi_init()
1184 		ispi->mem_ops = generic_mem_ops;  in intel_spi_init()
1187 	intel_spi_dump_regs(ispi);  in intel_spi_init()
1191 static bool intel_spi_is_protected(const struct intel_spi *ispi,  in intel_spi_is_protected()  argument
1196 	for (i = 0; i < ispi->pr_num; i++) {  in intel_spi_is_protected()
1199 		pr_value = readl(ispi->pregs + PR(i));  in intel_spi_is_protected()
1217 static void intel_spi_fill_partition(struct intel_spi *ispi,  in intel_spi_fill_partition()  argument
1233 	for (i = 1; i < ispi->nregions; i++) {  in intel_spi_fill_partition()
1236 		region = readl(ispi->base + FREG(i));  in intel_spi_fill_partition()
1250 		if (!writeable || intel_spi_is_protected(ispi, base, limit))  in intel_spi_fill_partition()
1259 static int intel_spi_read_desc(struct intel_spi *ispi)  in intel_spi_read_desc()  argument
1273 	ret = intel_spi_read(ispi, NULL, NULL, &op);  in intel_spi_read_desc()
1275 		dev_warn(ispi->dev, "failed to read descriptor\n");  in intel_spi_read_desc()
1279 	dev_dbg(ispi->dev, "FLVALSIG=0x%08x\n", buf[0]);  in intel_spi_read_desc()
1280 	dev_dbg(ispi->dev, "FLMAP0=0x%08x\n", buf[1]);  in intel_spi_read_desc()
1283 		dev_warn(ispi->dev, "descriptor signature not valid\n");  in intel_spi_read_desc()
1288 	dev_dbg(ispi->dev, "FCBA=%#x\n", fcba);  in intel_spi_read_desc()
1294 	ret = intel_spi_read(ispi, NULL, NULL, &op);  in intel_spi_read_desc()
1296 		dev_warn(ispi->dev, "failed to read FLCOMP\n");  in intel_spi_read_desc()
1300 	dev_dbg(ispi->dev, "FLCOMP=0x%08x\n", flcomp);  in intel_spi_read_desc()
1304 		ispi->chip0_size = SZ_512K;  in intel_spi_read_desc()
1307 		ispi->chip0_size = SZ_1M;  in intel_spi_read_desc()
1310 		ispi->chip0_size = SZ_2M;  in intel_spi_read_desc()
1313 		ispi->chip0_size = SZ_4M;  in intel_spi_read_desc()
1316 		ispi->chip0_size = SZ_8M;  in intel_spi_read_desc()
1319 		ispi->chip0_size = SZ_16M;  in intel_spi_read_desc()
1322 		ispi->chip0_size = SZ_32M;  in intel_spi_read_desc()
1325 		ispi->chip0_size = SZ_64M;  in intel_spi_read_desc()
1331 	dev_dbg(ispi->dev, "chip0 size %zd KB\n", ispi->chip0_size / SZ_1K);  in intel_spi_read_desc()
1335 		ispi->host->num_chipselect = 1;  in intel_spi_read_desc()
1337 		ispi->host->num_chipselect = 2;  in intel_spi_read_desc()
1341 	dev_dbg(ispi->dev, "%u flash components found\n",  in intel_spi_read_desc()
1342 		ispi->host->num_chipselect);  in intel_spi_read_desc()
1346 static int intel_spi_populate_chip(struct intel_spi *ispi)  in intel_spi_populate_chip()  argument
1352 	pdata = devm_kzalloc(ispi->dev, sizeof(*pdata), GFP_KERNEL);  in intel_spi_populate_chip()
1357 	pdata->parts = devm_kcalloc(ispi->dev, pdata->nr_parts,  in intel_spi_populate_chip()
1362 	intel_spi_fill_partition(ispi, pdata->parts);  in intel_spi_populate_chip()
1368 	if (!spi_new_device(ispi->host, &chip))  in intel_spi_populate_chip()
1371 	ret = intel_spi_read_desc(ispi);  in intel_spi_populate_chip()
1376 	if (ispi->host->num_chipselect < 2)  in intel_spi_populate_chip()
1382 	if (!spi_new_device(ispi->host, &chip))  in intel_spi_populate_chip()
1400 	struct intel_spi *ispi;  in intel_spi_probe()  local
1403 	host = devm_spi_alloc_host(dev, sizeof(*ispi));  in intel_spi_probe()
1409 	ispi = spi_controller_get_devdata(host);  in intel_spi_probe()
1411 	ispi->base = devm_ioremap_resource(dev, mem);  in intel_spi_probe()
1412 	if (IS_ERR(ispi->base))  in intel_spi_probe()
1413 		return PTR_ERR(ispi->base);  in intel_spi_probe()
1415 	ispi->dev = dev;  in intel_spi_probe()
1416 	ispi->host = host;  in intel_spi_probe()
1417 	ispi->info = info;  in intel_spi_probe()
1419 	ret = intel_spi_init(ispi);  in intel_spi_probe()
1427 	return intel_spi_populate_chip(ispi);  in intel_spi_probe()