126 #define CQSPI_REG_CONFIG			0x00  macro
304 	u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_is_idle()
475 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cqspi_enable_dtr()
494 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cqspi_enable_dtr()
811 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cqspi_controller_enable()
818 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cqspi_controller_enable()
847 	reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_versal_indirect_read_dma()
849 	writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_versal_indirect_read_dma()
912 	reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_versal_indirect_read_dma()
914 	writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_versal_indirect_read_dma()
945 	reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_versal_indirect_read_dma()
947 	writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_versal_indirect_read_dma()
1116 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cqspi_chipselect()
1135 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cqspi_chipselect()
1198 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cqspi_config_baudrate_div()
1201 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cqspi_config_baudrate_div()
1552 		reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_controller_init()
1554 		writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_controller_init()
1559 		reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_controller_init()
1561 		writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_controller_init()