1 // SPDX-License-Identifier: GPL-2.0-or-later
5  * QE UCC API Set - UCC specific routines implementations.
33 	if (ucc_num > UCC_MAX_NUM - 1)  in ucc_set_qe_mux_mii_mng()
34 		return -EINVAL;  in ucc_set_qe_mux_mii_mng()
37 	qe_clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,  in ucc_set_qe_mux_mii_mng()
50  * 'ucc_num' is the UCC number, from 0 - 7.
62 	case 0: guemr = &qe_immr->ucc1.slow.guemr;  in ucc_set_type()
64 	case 1: guemr = &qe_immr->ucc2.slow.guemr;  in ucc_set_type()
66 	case 2: guemr = &qe_immr->ucc3.slow.guemr;  in ucc_set_type()
68 	case 3: guemr = &qe_immr->ucc4.slow.guemr;  in ucc_set_type()
70 	case 4: guemr = &qe_immr->ucc5.slow.guemr;  in ucc_set_type()
72 	case 5: guemr = &qe_immr->ucc6.slow.guemr;  in ucc_set_type()
74 	case 6: guemr = &qe_immr->ucc7.slow.guemr;  in ucc_set_type()
76 	case 7: guemr = &qe_immr->ucc8.slow.guemr;  in ucc_set_type()
78 	default:  in ucc_set_type()
79 		return -EINVAL;  in ucc_set_type()
94 	*cmxucr = &qe_immr->qmx.cmxucr[cmx];  in get_cmxucr_reg()
95 	*shift = 16 - 8 * (ucc_num & 2);  in get_cmxucr_reg()
105 	if (ucc_num > UCC_MAX_NUM - 1)  in ucc_mux_set_grant_tsa_bkpt()
106 		return -EINVAL;  in ucc_mux_set_grant_tsa_bkpt()
119 	enum comm_dir mode)  in ucc_set_qe_mux_rxtx()  argument
127 	if (ucc_num > UCC_MAX_NUM - 1)  in ucc_set_qe_mux_rxtx()
128 		return -EINVAL;  in ucc_set_qe_mux_rxtx()
131 	if (!((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX)))  in ucc_set_qe_mux_rxtx()
132 		return -EINVAL;  in ucc_set_qe_mux_rxtx()
149 		default: break;  in ucc_set_qe_mux_rxtx()
164 		default: break;  in ucc_set_qe_mux_rxtx()
180 		default: break;  in ucc_set_qe_mux_rxtx()
196 		default: break;  in ucc_set_qe_mux_rxtx()
199 	default: break;  in ucc_set_qe_mux_rxtx()
204 		return -ENOENT;  in ucc_set_qe_mux_rxtx()
206 	if (mode == COMM_DIR_RX)  in ucc_set_qe_mux_rxtx()
217 	int clock_bits = -EINVAL;  in ucc_get_tdm_common_clk()
243 		default:  in ucc_get_tdm_common_clk()
264 		default:  in ucc_get_tdm_common_clk()
268 	default:  in ucc_get_tdm_common_clk()
277 	int clock_bits = -EINVAL;  in ucc_get_tdm_rx_clk()
288 		default:  in ucc_get_tdm_rx_clk()
300 		default:  in ucc_get_tdm_rx_clk()
312 		default:  in ucc_get_tdm_rx_clk()
324 		default:  in ucc_get_tdm_rx_clk()
336 		default:  in ucc_get_tdm_rx_clk()
348 		default:  in ucc_get_tdm_rx_clk()
360 		default:  in ucc_get_tdm_rx_clk()
372 		default:  in ucc_get_tdm_rx_clk()
383 	int clock_bits = -EINVAL;  in ucc_get_tdm_tx_clk()
394 		default:  in ucc_get_tdm_tx_clk()
406 		default:  in ucc_get_tdm_tx_clk()
418 		default:  in ucc_get_tdm_tx_clk()
430 		default:  in ucc_get_tdm_tx_clk()
442 		default:  in ucc_get_tdm_tx_clk()
454 		default:  in ucc_get_tdm_tx_clk()
466 		default:  in ucc_get_tdm_tx_clk()
478 		default:  in ucc_get_tdm_tx_clk()
487 /* tdm_num: TDM A-H port num is 0-7 */
488 static int ucc_get_tdm_rxtx_clk(enum comm_dir mode, u32 tdm_num,  in ucc_get_tdm_rxtx_clk()  argument
496 	if (mode == COMM_DIR_RX)  in ucc_get_tdm_rxtx_clk()
498 	if (mode == COMM_DIR_TX)  in ucc_get_tdm_rxtx_clk()
503 static u32 ucc_get_tdm_clk_shift(enum comm_dir mode, u32 tdm_num)  in ucc_get_tdm_clk_shift()  argument
507 	shift = (mode == COMM_DIR_RX) ? RX_CLK_SHIFT_BASE : TX_CLK_SHIFT_BASE;  in ucc_get_tdm_clk_shift()
509 		shift -= tdm_num * 4;  in ucc_get_tdm_clk_shift()
511 		shift -= (tdm_num - 4) * 4;  in ucc_get_tdm_clk_shift()
517 			 enum comm_dir mode)  in ucc_set_tdm_rxtx_clk()  argument
524 	qe_mux_reg = &qe_immr->qmx;  in ucc_set_tdm_rxtx_clk()
527 		return -EINVAL;  in ucc_set_tdm_rxtx_clk()
530 	if (mode != COMM_DIR_RX && mode != COMM_DIR_TX)  in ucc_set_tdm_rxtx_clk()
531 		return -EINVAL;  in ucc_set_tdm_rxtx_clk()
533 	clock_bits = ucc_get_tdm_rxtx_clk(mode, tdm_num, clock);  in ucc_set_tdm_rxtx_clk()
535 		return -EINVAL;  in ucc_set_tdm_rxtx_clk()
537 	shift = ucc_get_tdm_clk_shift(mode, tdm_num);  in ucc_set_tdm_rxtx_clk()
539 	cmxs1cr = (tdm_num < 4) ? &qe_mux_reg->cmxsi1cr_l :  in ucc_set_tdm_rxtx_clk()
540 				  &qe_mux_reg->cmxsi1cr_h;  in ucc_set_tdm_rxtx_clk()
549 				   enum comm_dir mode)  in ucc_get_tdm_sync_source()  argument
551 	int source = -EINVAL;  in ucc_get_tdm_sync_source()
553 	if (mode == COMM_DIR_RX && clock == QE_RSYNC_PIN) {  in ucc_get_tdm_sync_source()
557 	if (mode == COMM_DIR_TX && clock == QE_TSYNC_PIN) {  in ucc_get_tdm_sync_source()
572 		default:  in ucc_get_tdm_sync_source()
585 		default:  in ucc_get_tdm_sync_source()
598 		default:  in ucc_get_tdm_sync_source()
611 		default:  in ucc_get_tdm_sync_source()
620 static u32 ucc_get_tdm_sync_shift(enum comm_dir mode, u32 tdm_num)  in ucc_get_tdm_sync_shift()  argument
624 	shift = (mode == COMM_DIR_RX) ? RX_SYNC_SHIFT_BASE : TX_SYNC_SHIFT_BASE;  in ucc_get_tdm_sync_shift()
625 	shift -= tdm_num * 2;  in ucc_get_tdm_sync_shift()
631 			  enum comm_dir mode)  in ucc_set_tdm_rxtx_sync()  argument
637 	qe_mux_reg = &qe_immr->qmx;  in ucc_set_tdm_rxtx_sync()
640 		return -EINVAL;  in ucc_set_tdm_rxtx_sync()
643 	if (mode != COMM_DIR_RX && mode != COMM_DIR_TX)  in ucc_set_tdm_rxtx_sync()
644 		return -EINVAL;  in ucc_set_tdm_rxtx_sync()
646 	source = ucc_get_tdm_sync_source(tdm_num, clock, mode);  in ucc_set_tdm_rxtx_sync()
648 		return -EINVAL;  in ucc_set_tdm_rxtx_sync()
650 	shift = ucc_get_tdm_sync_shift(mode, tdm_num);  in ucc_set_tdm_rxtx_sync()
652 	qe_clrsetbits_be32(&qe_mux_reg->cmxsi1syr,  in ucc_set_tdm_rxtx_sync()