1 // SPDX-License-Identifier: GPL-2.0-or-later
5  * QE UCC API Set - UCC specific routines implementations.
33 	if (ucc_num > UCC_MAX_NUM - 1)  in ucc_set_qe_mux_mii_mng()
34 		return -EINVAL;  in ucc_set_qe_mux_mii_mng()
37 	qe_clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,  in ucc_set_qe_mux_mii_mng()
50  * 'ucc_num' is the UCC number, from 0 - 7.
61 	switch (ucc_num) {  in ucc_set_type()
62 	case 0: guemr = &qe_immr->ucc1.slow.guemr;  in ucc_set_type()
64 	case 1: guemr = &qe_immr->ucc2.slow.guemr;  in ucc_set_type()
66 	case 2: guemr = &qe_immr->ucc3.slow.guemr;  in ucc_set_type()
68 	case 3: guemr = &qe_immr->ucc4.slow.guemr;  in ucc_set_type()
70 	case 4: guemr = &qe_immr->ucc5.slow.guemr;  in ucc_set_type()
72 	case 5: guemr = &qe_immr->ucc6.slow.guemr;  in ucc_set_type()
74 	case 6: guemr = &qe_immr->ucc7.slow.guemr;  in ucc_set_type()
76 	case 7: guemr = &qe_immr->ucc8.slow.guemr;  in ucc_set_type()
79 		return -EINVAL;  in ucc_set_type()
94 	*cmxucr = &qe_immr->qmx.cmxucr[cmx];  in get_cmxucr_reg()
95 	*shift = 16 - 8 * (ucc_num & 2);  in get_cmxucr_reg()
105 	if (ucc_num > UCC_MAX_NUM - 1)  in ucc_mux_set_grant_tsa_bkpt()
106 		return -EINVAL;  in ucc_mux_set_grant_tsa_bkpt()
127 	if (ucc_num > UCC_MAX_NUM - 1)  in ucc_set_qe_mux_rxtx()
128 		return -EINVAL;  in ucc_set_qe_mux_rxtx()
132 		return -EINVAL;  in ucc_set_qe_mux_rxtx()
136 	switch (reg_num) {  in ucc_set_qe_mux_rxtx()
138 		switch (clock) {  in ucc_set_qe_mux_rxtx()
142 		case QE_BRG8:	clock_bits = 4; break;  in ucc_set_qe_mux_rxtx()
153 		switch (clock) {  in ucc_set_qe_mux_rxtx()
157 		case QE_BRG8:	clock_bits = 4; break;  in ucc_set_qe_mux_rxtx()
168 		switch (clock) {  in ucc_set_qe_mux_rxtx()
172 		case QE_BRG16:	clock_bits = 4; break;  in ucc_set_qe_mux_rxtx()
183 	case 4:  in ucc_set_qe_mux_rxtx()
184 		switch (clock) {  in ucc_set_qe_mux_rxtx()
188 		case QE_BRG16:	clock_bits = 4; break;  in ucc_set_qe_mux_rxtx()
204 		return -ENOENT;  in ucc_set_qe_mux_rxtx()
207 		shift += 4;  in ucc_set_qe_mux_rxtx()
217 	int clock_bits = -EINVAL;  in ucc_get_tdm_common_clk()
221 	 * clock source BRG3,4 and CLK1,2  in ucc_get_tdm_common_clk()
222 	 * for TDM[4, 5, 6, 7], TX and RX use  common  in ucc_get_tdm_common_clk()
225 	switch (tdm_num) {  in ucc_get_tdm_common_clk()
230 		switch (clock) {  in ucc_get_tdm_common_clk()
238 			clock_bits = 4;  in ucc_get_tdm_common_clk()
247 	case 4:  in ucc_get_tdm_common_clk()
251 		switch (clock) {  in ucc_get_tdm_common_clk()
259 			clock_bits = 4;  in ucc_get_tdm_common_clk()
277 	int clock_bits = -EINVAL;  in ucc_get_tdm_rx_clk()
279 	switch (tdm_num) {  in ucc_get_tdm_rx_clk()
281 		switch (clock) {  in ucc_get_tdm_rx_clk()
293 		switch (clock) {  in ucc_get_tdm_rx_clk()
305 		switch (clock) {  in ucc_get_tdm_rx_clk()
317 		switch (clock) {  in ucc_get_tdm_rx_clk()
328 	case 4:  in ucc_get_tdm_rx_clk()
329 		switch (clock) {  in ucc_get_tdm_rx_clk()
341 		switch (clock) {  in ucc_get_tdm_rx_clk()
353 		switch (clock) {  in ucc_get_tdm_rx_clk()
365 		switch (clock) {  in ucc_get_tdm_rx_clk()
383 	int clock_bits = -EINVAL;  in ucc_get_tdm_tx_clk()
385 	switch (tdm_num) {  in ucc_get_tdm_tx_clk()
387 		switch (clock) {  in ucc_get_tdm_tx_clk()
399 		switch (clock) {  in ucc_get_tdm_tx_clk()
411 		switch (clock) {  in ucc_get_tdm_tx_clk()
423 		switch (clock) {  in ucc_get_tdm_tx_clk()
434 	case 4:  in ucc_get_tdm_tx_clk()
435 		switch (clock) {  in ucc_get_tdm_tx_clk()
447 		switch (clock) {  in ucc_get_tdm_tx_clk()
459 		switch (clock) {  in ucc_get_tdm_tx_clk()
471 		switch (clock) {  in ucc_get_tdm_tx_clk()
487 /* tdm_num: TDM A-H port num is 0-7 */
508 	if (tdm_num < 4)  in ucc_get_tdm_clk_shift()
509 		shift -= tdm_num * 4;  in ucc_get_tdm_clk_shift()
511 		shift -= (tdm_num - 4) * 4;  in ucc_get_tdm_clk_shift()
524 	qe_mux_reg = &qe_immr->qmx;  in ucc_set_tdm_rxtx_clk()
527 		return -EINVAL;  in ucc_set_tdm_rxtx_clk()
531 		return -EINVAL;  in ucc_set_tdm_rxtx_clk()
535 		return -EINVAL;  in ucc_set_tdm_rxtx_clk()
539 	cmxs1cr = (tdm_num < 4) ? &qe_mux_reg->cmxsi1cr_l :  in ucc_set_tdm_rxtx_clk()
540 				  &qe_mux_reg->cmxsi1cr_h;  in ucc_set_tdm_rxtx_clk()
551 	int source = -EINVAL;  in ucc_get_tdm_sync_source()
562 	switch (tdm_num) {  in ucc_get_tdm_sync_source()
565 		switch (clock) {  in ucc_get_tdm_sync_source()
578 		switch (clock) {  in ucc_get_tdm_sync_source()
589 	case 4:  in ucc_get_tdm_sync_source()
591 		switch (clock) {  in ucc_get_tdm_sync_source()
604 		switch (clock) {  in ucc_get_tdm_sync_source()
625 	shift -= tdm_num * 2;  in ucc_get_tdm_sync_shift()
637 	qe_mux_reg = &qe_immr->qmx;  in ucc_set_tdm_rxtx_sync()
640 		return -EINVAL;  in ucc_set_tdm_rxtx_sync()
644 		return -EINVAL;  in ucc_set_tdm_rxtx_sync()
648 		return -EINVAL;  in ucc_set_tdm_rxtx_sync()
652 	qe_clrsetbits_be32(&qe_mux_reg->cmxsi1syr,  in ucc_set_tdm_rxtx_sync()