2721 		if (rd_reg_word(&reg->mailbox12) & BIT_0)  in qla2x00_initialize_adapter()
2859 	ha->pci_attr = rd_reg_word(&reg->ctrl_status);  in qla2100_pci_config()
2903 			if ((rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) != 0)  in qla2300_pci_config()
2911 		rd_reg_word(&reg->ctrl_status);  in qla2300_pci_config()
2921 		rd_reg_word(&reg->ctrl_status);  in qla2300_pci_config()
2926 			if ((rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) == 0)  in qla2300_pci_config()
2941 	ha->pci_attr = rd_reg_word(&reg->ctrl_status);  in qla2300_pci_config()
3092 				if ((rd_reg_word(&reg->hccr) &  in qla2x00_reset_chip()
3098 			rd_reg_word(&reg->hccr);	/* PCI Posting. */  in qla2x00_reset_chip()
3104 		rd_reg_word(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_reset_chip()
3108 		rd_reg_word(&reg->fpm_diag_config);	/* PCI Posting. */  in qla2x00_reset_chip()
3113 			rd_reg_word(&reg->fpm_diag_config); /* PCI Posting. */  in qla2x00_reset_chip()
3118 		rd_reg_word(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_reset_chip()
3137 		rd_reg_word(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_reset_chip()
3141 		rd_reg_word(&reg->hccr);		/* PCI Posting. */  in qla2x00_reset_chip()
3145 		rd_reg_word(&reg->hccr);		/* PCI Posting. */  in qla2x00_reset_chip()
3163 			if ((rd_reg_word(&reg->ctrl_status) &  in qla2x00_reset_chip()
3178 	rd_reg_word(&reg->hccr);			/* PCI Posting. */  in qla2x00_reset_chip()
3197 		rd_reg_word(&reg->hccr);		/* PCI Posting. */  in qla2x00_reset_chip()
3236 	mb[0] = rd_reg_word(mbptr);  in qla_chk_risc_recovery()
3242 			mb[i] = rd_reg_word(mbptr);  in qla_chk_risc_recovery()
3310 	rd_reg_word(&reg->mailbox0);  in qla24xx_reset_risc()
3311 	for (cnt = 10000; rd_reg_word(&reg->mailbox0) != 0 &&  in qla24xx_reset_risc()
3326 	    rd_reg_word(&reg->mailbox0));  in qla24xx_reset_risc()
3373 	wd = rd_reg_word(&reg->mailbox0);  in qla24xx_reset_risc()
3381 			wd = rd_reg_word(&reg->mailbox0);  in qla24xx_reset_risc()
3396 	     rd_reg_word(&reg->mailbox0));  in qla24xx_reset_risc()
3553 		data = rd_reg_word(&reg->ctrl_status);  in qla2x00_chip_diag()
4272 		rd_reg_word(&reg->hccr);  in qla2x00_setup_chip()
4383 		rd_reg_word(&reg->hccr);  in qla2x00_setup_chip()
4644 	rd_reg_word(ISP_RSP_Q_OUT(ha, reg));		/* PCI Posting. */  in qla2x00_config_rings()
4728 	rd_reg_word(&ioreg->hccr);  in qla24xx_config_rings()
5215 		if ((rd_reg_word(&reg->ctrl_status) >> 14) == 1)  in qla2x00_nvram_config()
7793 	rd_reg_word(&reg->hccr);			/* PCI Posting. */  in qla2x00_reset_adapter()
7795 	rd_reg_word(&reg->hccr);			/* PCI Posting. */  in qla2x00_reset_adapter()