2985 	ha->pci_attr = rd_reg_dword(&reg->ctrl_status);  in qla24xx_pci_config()
3288 		if ((rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)  in qla24xx_reset_risc()
3294 	if (!(rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE))  in qla24xx_reset_risc()
3299 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
3300 	    rd_reg_dword(&reg->ctrl_status),  in qla24xx_reset_risc()
3301 	    (rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE));  in qla24xx_reset_risc()
3325 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
3329 	rd_reg_dword(&reg->ctrl_status);  in qla24xx_reset_risc()
3332 		if ((rd_reg_dword(&reg->ctrl_status) &  in qla24xx_reset_risc()
3338 	if (!(rd_reg_dword(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))  in qla24xx_reset_risc()
3343 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
3344 	    rd_reg_dword(&reg->ctrl_status));  in qla24xx_reset_risc()
3364 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_risc()
3367 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_risc()
3371 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_risc()
3395 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
3416 	*data = rd_reg_dword(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFSET);  in qla25xx_read_risc_sema_reg()
7816 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_adapter()
7818 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_adapter()