Lines Matching refs:RD_REG_WORD
729 ha->mailbox_out[0] = RD_REG_WORD(®->mailbox0); in qla1280_mailbox_timeout()
732 RD_REG_WORD(®->ictrl), RD_REG_WORD(®->istatus)); in qla1280_mailbox_timeout()
830 RD_REG_WORD(&ha->iobase->istatus)); in qla1280_error_action()
833 RD_REG_WORD(&ha->iobase->host_cmd), in qla1280_error_action()
834 RD_REG_WORD(&ha->iobase->ictrl), jiffies); in qla1280_error_action()
1053 RD_REG_WORD(&ha->iobase->ictrl); /* PCI Posted Write flush */ in qla1280_disable_intrs()
1061 RD_REG_WORD(&ha->iobase->ictrl); /* PCI Posted Write flush */ in qla1280_enable_intrs()
1422 RD_REG_WORD(®->host_cmd); in qla1280_initialize_adapter()
1571 data = RD_REG_WORD(®->ictrl); in qla1280_chip_diag()
1587 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_chip_diag()
1595 data = RD_REG_WORD(®->mailbox0); in qla1280_chip_diag()
1604 if (RD_REG_WORD(®->mailbox1) != PROD_ID_1 || in qla1280_chip_diag()
1605 (RD_REG_WORD(®->mailbox2) != PROD_ID_2 && in qla1280_chip_diag()
1606 RD_REG_WORD(®->mailbox2) != PROD_ID_2a) || in qla1280_chip_diag()
1607 RD_REG_WORD(®->mailbox3) != PROD_ID_3 || in qla1280_chip_diag()
1608 RD_REG_WORD(®->mailbox4) != PROD_ID_4) { in qla1280_chip_diag()
1611 RD_REG_WORD(®->mailbox1), in qla1280_chip_diag()
1612 RD_REG_WORD(®->mailbox2), in qla1280_chip_diag()
1613 RD_REG_WORD(®->mailbox3), in qla1280_chip_diag()
1614 RD_REG_WORD(®->mailbox4)); in qla1280_chip_diag()
2179 hwrev = RD_REG_WORD(®->cfg_0) & ISP_CFG0_HWMSK; in qla1280_nvram_config()
2181 cfg1 = RD_REG_WORD(®->cfg_1) & ~(BIT_4 | BIT_5 | BIT_6); in qla1280_nvram_config()
2182 cdma_conf = RD_REG_WORD(®->cdma_cfg); in qla1280_nvram_config()
2210 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_nvram_config()
2213 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_nvram_config()
2359 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_nvram_request()
2362 reg_data = RD_REG_WORD(®->nvram); in qla1280_nvram_request()
2366 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_nvram_request()
2373 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_nvram_request()
2385 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_nv_write()
2388 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_nv_write()
2391 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_nv_write()
2466 mb[0], ha->mailbox_out[0], RD_REG_WORD(®->istatus)); in qla1280_mailbox_command()
2468 RD_REG_WORD(®->mailbox0), RD_REG_WORD(®->mailbox1), in qla1280_mailbox_command()
2469 RD_REG_WORD(®->mailbox2), RD_REG_WORD(®->mailbox3)); in qla1280_mailbox_command()
2471 RD_REG_WORD(®->mailbox4), RD_REG_WORD(®->mailbox5), in qla1280_mailbox_command()
2472 RD_REG_WORD(®->mailbox6), RD_REG_WORD(®->mailbox7)); in qla1280_mailbox_command()
2510 data = RD_REG_WORD(®->istatus); in qla1280_poll()
2680 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_reset_adapter()
2764 cnt = RD_REG_WORD(®->mailbox4); in qla1280_64bit_start_scsi()
3026 cnt = RD_REG_WORD(®->mailbox4); in qla1280_32bit_start_scsi()
3243 cnt = RD_REG_WORD(®->mailbox4); in qla1280_req_pkt()
3346 istatus = RD_REG_WORD(®->istatus); in qla1280_isr()
3351 mailbox[5] = RD_REG_WORD(®->mailbox5); in qla1280_isr()
3362 *wptr++ = RD_REG_WORD(®->mailbox0); in qla1280_isr()
3363 *wptr++ = RD_REG_WORD(®->mailbox1); in qla1280_isr()
3364 *wptr = RD_REG_WORD(®->mailbox2); in qla1280_isr()
3367 *wptr++ = RD_REG_WORD(®->mailbox3); in qla1280_isr()
3368 *wptr++ = RD_REG_WORD(®->mailbox4); in qla1280_isr()
3370 *wptr++ = RD_REG_WORD(®->mailbox6); in qla1280_isr()
3371 *wptr = RD_REG_WORD(®->mailbox7); in qla1280_isr()
3766 RD_REG_WORD(®->id_l); in qla1280_abort_isp()
3830 ret = RD_REG_WORD(addr); in qla1280_debounce_register()
3831 ret2 = RD_REG_WORD(addr); in qla1280_debounce_register()
3838 ret = RD_REG_WORD(addr); in qla1280_debounce_register()
3839 ret2 = RD_REG_WORD(addr); in qla1280_debounce_register()
3861 config_reg = RD_REG_WORD(®->cfg_1); in qla1280_check_for_dead_scsi_bus()
3863 scsi_control = RD_REG_WORD(®->scsiControlPins); in qla1280_check_for_dead_scsi_bus()