2052 			  (unsigned long)ha->mem_ptr);  in ips_host_info()
2252 			writel(0, ha->mem_ptr + IPS_REG_FLAP);  in ips_get_bios_version()
2256 			if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)  in ips_get_bios_version()
2259 			writel(1, ha->mem_ptr + IPS_REG_FLAP);  in ips_get_bios_version()
2263 			if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)  in ips_get_bios_version()
2267 			writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);  in ips_get_bios_version()
2271 			major = readb(ha->mem_ptr + IPS_REG_FLDP);  in ips_get_bios_version()
2274 			writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);  in ips_get_bios_version()
2277 			minor = readb(ha->mem_ptr + IPS_REG_FLDP);  in ips_get_bios_version()
2280 			writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);  in ips_get_bios_version()
2283 			subminor = readb(ha->mem_ptr + IPS_REG_FLDP);  in ips_get_bios_version()
4258 		if (ha->mem_ptr) {  in ips_free()
4261 			ha->mem_ptr = NULL;  in ips_free()
4504 	isr = readb(ha->mem_ptr + IPS_REG_HISR);  in ips_isinit_copperhead_memio()
4505 	scpr = readb(ha->mem_ptr + IPS_REG_SCPR);  in ips_isinit_copperhead_memio()
4533 	post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);  in ips_isinit_morpheus()
4534 	bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR);  in ips_isinit_morpheus()
4663 	writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);  in ips_enable_int_copperhead_memio()
4664 	readb(ha->mem_ptr + IPS_REG_HISR);	/*Ensure PCI Posting Completes*/  in ips_enable_int_copperhead_memio()
4682 	Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);  in ips_enable_int_morpheus()
4684 	writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);  in ips_enable_int_morpheus()
4685 	readl(ha->mem_ptr + IPS_REG_I960_OIMR);	/*Ensure PCI Posting Completes*/  in ips_enable_int_morpheus()
4802 			Isr = readb(ha->mem_ptr + IPS_REG_HISR);  in ips_init_copperhead_memio()
4814 		PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);  in ips_init_copperhead_memio()
4815 		writeb(Isr, ha->mem_ptr + IPS_REG_HISR);  in ips_init_copperhead_memio()
4828 			Isr = readb(ha->mem_ptr + IPS_REG_HISR);  in ips_init_copperhead_memio()
4840 		readb(ha->mem_ptr + IPS_REG_ISPR);  in ips_init_copperhead_memio()
4841 		writeb(Isr, ha->mem_ptr + IPS_REG_HISR);  in ips_init_copperhead_memio()
4845 		Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP);  in ips_init_copperhead_memio()
4859 	writel(0x1010, ha->mem_ptr + IPS_REG_CCCR);  in ips_init_copperhead_memio()
4862 	writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR);  in ips_init_copperhead_memio()
4866 		writel(0, ha->mem_ptr + IPS_REG_NDAE);  in ips_init_copperhead_memio()
4869 	writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);  in ips_init_copperhead_memio()
4897 		Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);  in ips_init_morpheus()
4914 	Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);  in ips_init_morpheus()
4922 		writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);  in ips_init_morpheus()
4925 			Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);  in ips_init_morpheus()
4942 	writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);  in ips_init_morpheus()
4953 		Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);  in ips_init_morpheus()
4970 	Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1);  in ips_init_morpheus()
4974 	writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);  in ips_init_morpheus()
4977 	Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);  in ips_init_morpheus()
4979 	writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);  in ips_init_morpheus()
5061 		writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR);  in ips_reset_copperhead_memio()
5066 		writeb(0, ha->mem_ptr + IPS_REG_SCPR);  in ips_reset_copperhead_memio()
5107 		writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR);  in ips_reset_morpheus()
5178 	writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR);  in ips_statinit_memio()
5180 	       ha->mem_ptr + IPS_REG_SQER);  in ips_statinit_memio()
5181 	writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR);  in ips_statinit_memio()
5182 	writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR);  in ips_statinit_memio()
5237 	writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR);  in ips_statupd_copperhead_memio()
5258 	val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ);  in ips_statupd_morpheus()
5348 	while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) {  in ips_issue_copperhead_memio()
5364 	writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR);  in ips_issue_copperhead_memio()
5365 	writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR);  in ips_issue_copperhead_memio()
5429 	writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ);  in ips_issue_i2o_memio()
5483 	Isr = readb(ha->mem_ptr + IPS_REG_HISR);  in ips_isintr_copperhead_memio()
5494 		writeb(Isr, ha->mem_ptr + IPS_REG_HISR);  in ips_isintr_copperhead_memio()
5516 	Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);  in ips_isintr_morpheus()
6136 	writel(0, ha->mem_ptr + IPS_REG_FLAP);  in ips_erase_bios_memio()
6140 	writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);  in ips_erase_bios_memio()
6145 	writeb(0x20, ha->mem_ptr + IPS_REG_FLDP);  in ips_erase_bios_memio()
6150 	writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP);  in ips_erase_bios_memio()
6155 	writeb(0x70, ha->mem_ptr + IPS_REG_FLDP);  in ips_erase_bios_memio()
6163 			writel(0, ha->mem_ptr + IPS_REG_FLAP);  in ips_erase_bios_memio()
6167 		status = readb(ha->mem_ptr + IPS_REG_FLDP);  in ips_erase_bios_memio()
6181 		writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP);  in ips_erase_bios_memio()
6189 				writel(0, ha->mem_ptr + IPS_REG_FLAP);  in ips_erase_bios_memio()
6193 			status = readb(ha->mem_ptr + IPS_REG_FLDP);  in ips_erase_bios_memio()
6217 	writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);  in ips_erase_bios_memio()
6222 	writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);  in ips_erase_bios_memio()
6342 		writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);  in ips_program_bios_memio()
6346 		writeb(0x40, ha->mem_ptr + IPS_REG_FLDP);  in ips_program_bios_memio()
6350 		writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP);  in ips_program_bios_memio()
6358 				writel(0, ha->mem_ptr + IPS_REG_FLAP);  in ips_program_bios_memio()
6362 			status = readb(ha->mem_ptr + IPS_REG_FLDP);  in ips_program_bios_memio()
6373 			writel(0, ha->mem_ptr + IPS_REG_FLAP);  in ips_program_bios_memio()
6377 			writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);  in ips_program_bios_memio()
6387 			writel(0, ha->mem_ptr + IPS_REG_FLAP);  in ips_program_bios_memio()
6391 			writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);  in ips_program_bios_memio()
6400 	writel(0, ha->mem_ptr + IPS_REG_FLAP);  in ips_program_bios_memio()
6404 	writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);  in ips_program_bios_memio()
6478 	writel(0, ha->mem_ptr + IPS_REG_FLAP);  in ips_verify_bios_memio()
6482 	if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)  in ips_verify_bios_memio()
6485 	writel(1, ha->mem_ptr + IPS_REG_FLAP);  in ips_verify_bios_memio()
6488 	if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)  in ips_verify_bios_memio()
6494 		writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);  in ips_verify_bios_memio()
6499 		    (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP);  in ips_verify_bios_memio()
6843 	char __iomem *mem_ptr;  in ips_init_phase1()  local
6887 		mem_ptr = ioremap_ptr + offs;  in ips_init_phase1()
6890 		mem_ptr = NULL;  in ips_init_phase1()
6910 	ha->mem_ptr = mem_ptr;  in ips_init_phase1()
7012 		IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1);  in ips_init_phase1()