Lines Matching refs:host_int_mask

1359 		orig_mask = readl(&reg->host_int_mask); /* disable outbound message0 int */  in arcmsr_disable_outbound_ints()
1360 		writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);  in arcmsr_disable_outbound_ints()
1372 		orig_mask = readl(&reg->host_int_mask);  in arcmsr_disable_outbound_ints()
1373 …k | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR, &reg->host_int_mask);  in arcmsr_disable_outbound_ints()
1374 		readl(&reg->host_int_mask); /* Dummy readl to force pci flush */  in arcmsr_disable_outbound_ints()
1761 		writel(intmask_org & mask, &reg->host_int_mask);  in arcmsr_enable_outbound_ints()
1777 		writel(intmask_org & mask, &reg->host_int_mask);  in arcmsr_enable_outbound_ints()
3358 	intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */  in arcmsr_hbaC_get_config()
3359 	writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);  in arcmsr_hbaC_get_config()
3403 	intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */  in arcmsr_hbaE_get_config()
3404 	writel(intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE, &reg->host_int_mask);  in arcmsr_hbaE_get_config()
3429 	intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */  in arcmsr_hbaF_get_config()
3430 	writel(intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE, &reg->host_int_mask);  in arcmsr_hbaF_get_config()