Lines Matching refs:Q6SS_GFMUX_CTL_REG
29 #define Q6SS_GFMUX_CTL_REG 0x020 macro
226 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_reset()
228 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_reset()
400 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_qcs404_power_on()
402 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_qcs404_power_on()
412 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_qcs404_power_on()
414 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_qcs404_power_on()
569 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_qcs404_wcss_shutdown()
571 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_qcs404_wcss_shutdown()
650 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_q6_powerdown()
652 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_q6_powerdown()