70 #define QDSP6SS_PWR_CTL_REG		0x030  macro
736 		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
738 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
739 		val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
754 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
760 			val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
762 			writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
766 			writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
792 			val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
795 			writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
800 				writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
805 		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
807 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
815 		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
817 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
818 		val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
824 		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
827 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
829 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
831 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
833 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
837 	writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
1257 		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5_mba_reclaim()
1260 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5_mba_reclaim()