Lines Matching refs:ENABLE_MASK
75 #define ENABLE_MASK(id) (BIT(id) | BIT(4 + (id))) macro
147 .enable_mask = ENABLE_MASK(ctrl_bit),\
148 .enable_val = ENABLE_MASK(ctrl_bit),\
1244 .enable_mask = ENABLE_MASK(RK817_ID_DCDC1),
1245 .enable_val = ENABLE_MASK(RK817_ID_DCDC1),
1267 .enable_mask = ENABLE_MASK(RK817_ID_DCDC2),
1268 .enable_val = ENABLE_MASK(RK817_ID_DCDC2),
1290 .enable_mask = ENABLE_MASK(RK817_ID_DCDC3),
1291 .enable_val = ENABLE_MASK(RK817_ID_DCDC3),
1313 .enable_mask = ENABLE_MASK(RK817_ID_DCDC4),
1314 .enable_val = ENABLE_MASK(RK817_ID_DCDC4),
1337 .enable_mask = ENABLE_MASK(1),
1338 .enable_val = ENABLE_MASK(1),
1345 RK817_POWER_EN_REG(1), ENABLE_MASK(0),
1349 RK817_POWER_EN_REG(1), ENABLE_MASK(1),
1353 RK817_POWER_EN_REG(1), ENABLE_MASK(2),
1357 RK817_POWER_EN_REG(1), ENABLE_MASK(3),
1361 RK817_POWER_EN_REG(2), ENABLE_MASK(0),
1365 RK817_POWER_EN_REG(2), ENABLE_MASK(1),
1369 RK817_POWER_EN_REG(2), ENABLE_MASK(2),
1373 RK817_POWER_EN_REG(2), ENABLE_MASK(3),
1377 RK817_POWER_EN_REG(3), ENABLE_MASK(0),
1380 RK817_POWER_EN_REG(3), ENABLE_MASK(2),
1383 RK817_POWER_EN_REG(3), ENABLE_MASK(3),
1402 .enable_mask = ENABLE_MASK(RK817_ID_DCDC1),
1403 .enable_val = ENABLE_MASK(RK817_ID_DCDC1),
1425 .enable_mask = ENABLE_MASK(RK817_ID_DCDC2),
1426 .enable_val = ENABLE_MASK(RK817_ID_DCDC2),
1448 .enable_mask = ENABLE_MASK(RK817_ID_DCDC3),
1449 .enable_val = ENABLE_MASK(RK817_ID_DCDC3),
1471 .enable_mask = ENABLE_MASK(RK817_ID_DCDC4),
1472 .enable_val = ENABLE_MASK(RK817_ID_DCDC4),
1483 RK817_POWER_EN_REG(1), ENABLE_MASK(0),
1487 RK817_POWER_EN_REG(1), ENABLE_MASK(1),
1491 RK817_POWER_EN_REG(1), ENABLE_MASK(2),
1495 RK817_POWER_EN_REG(1), ENABLE_MASK(3),
1499 RK817_POWER_EN_REG(2), ENABLE_MASK(0),
1503 RK817_POWER_EN_REG(2), ENABLE_MASK(1),
1507 RK817_POWER_EN_REG(2), ENABLE_MASK(2),
1511 RK817_POWER_EN_REG(2), ENABLE_MASK(3),
1515 RK817_POWER_EN_REG(3), ENABLE_MASK(0),
1519 RK817_POWER_EN_REG(3), ENABLE_MASK(1), ENABLE_MASK(1),
1522 RK817_POWER_EN_REG(3), ENABLE_MASK(2),