Lines Matching refs:POWER_LIMIT1
108 [POWER_LIMIT1] = "long_term",
124 if (pl < POWER_LIMIT1 || pl > POWER_LIMIT4) in is_pl_valid()
132 if (pl == POWER_LIMIT1) in get_pl_lock_prim()
156 case POWER_LIMIT1: in get_pl_prim()
162 return POWER_LIMIT1; in get_pl_prim()
343 ret = rapl_write_pl_data(rd, POWER_LIMIT1, PL_ENABLE, mode); in set_domain_enable()
357 if (rd->rpl[POWER_LIMIT1].locked) { in get_domain_enable()
362 ret = rapl_read_pl_data(rd, POWER_LIMIT1, PL_ENABLE, true, &val); in get_domain_enable()
423 for (i = POWER_LIMIT1, j = 0; i < NR_POWER_LIMITS; i++) { in contraint_to_pl()
594 rp->priv->limits[i] |= BIT(POWER_LIMIT1); in rapl_init_domains()
596 for (t = POWER_LIMIT1; t < NR_POWER_LIMITS; t++) { in rapl_init_domains()
641 [POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0,
697 [POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, TPMI_POWER_LIMIT_MASK, 0,
777 case POWER_LIMIT1: in prim_fixups()
1039 rapl_write_pl_data(rd, POWER_LIMIT1, PL_CLAMP, mode); in set_floor_freq_default()
1450 for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++) { in rapl_detect_powerlimit()
1511 for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++) { in rapl_remove_package()
1614 for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++) { in power_limit_state_save()
1635 for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++) in power_limit_state_restore()