Lines Matching +full:irq +full:- +full:syscfg
1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/irq.h>
28 #include <linux/pinctrl/pinconf-generic.h>
35 #include "../pinctrl-utils.h"
36 #include "pinctrl-stm32.h"
149 return function - 1; in stm32_gpio_get_alt()
160 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); in stm32_gpio_backup_value()
161 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; in stm32_gpio_backup_value()
167 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | in stm32_gpio_backup_mode()
169 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; in stm32_gpio_backup_mode()
170 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; in stm32_gpio_backup_mode()
176 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); in stm32_gpio_backup_driving()
177 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; in stm32_gpio_backup_driving()
183 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK; in stm32_gpio_backup_speed()
184 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT; in stm32_gpio_backup_speed()
190 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK; in stm32_gpio_backup_bias()
191 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT; in stm32_gpio_backup_bias()
204 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); in __stm32_gpio_set()
210 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_request()
212 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); in stm32_gpio_request()
214 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin); in stm32_gpio_request()
216 dev_err(pctl->dev, "pin %d not in range.\n", pin); in stm32_gpio_request()
217 return -EINVAL; in stm32_gpio_request()
220 return pinctrl_gpio_request(chip->base + offset); in stm32_gpio_request()
225 pinctrl_gpio_free(chip->base + offset); in stm32_gpio_free()
232 return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); in stm32_gpio_get()
244 return pinctrl_gpio_direction_input(chip->base + offset); in stm32_gpio_direction_input()
253 pinctrl_gpio_direction_output(chip->base + offset); in stm32_gpio_direction_output()
264 fwspec.fwnode = bank->fwnode; in stm32_gpio_to_irq()
285 ret = -EINVAL; in stm32_gpio_get_direction()
295 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_init_valid_mask()
302 if (bank->secure_control) { in stm32_gpio_init_valid_mask()
304 sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR); in stm32_gpio_init_valid_mask()
309 dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i); in stm32_gpio_init_valid_mask()
332 struct stm32_gpio_bank *bank = d->domain->host_data; in stm32_gpio_irq_trigger()
335 /* Do not access the GPIO if this is not LEVEL triggered IRQ. */ in stm32_gpio_irq_trigger()
336 if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK)) in stm32_gpio_irq_trigger()
340 level = stm32_gpio_get(&bank->gpio_chip, d->hwirq); in stm32_gpio_irq_trigger()
341 if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) || in stm32_gpio_irq_trigger()
342 (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH)) in stm32_gpio_irq_trigger()
354 struct stm32_gpio_bank *bank = d->domain->host_data; in stm32_gpio_set_type()
370 return -EINVAL; in stm32_gpio_set_type()
373 bank->irq_type[d->hwirq] = type; in stm32_gpio_set_type()
380 struct stm32_gpio_bank *bank = irq_data->domain->host_data; in stm32_gpio_irq_request_resources()
381 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_irq_request_resources()
384 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_request_resources()
388 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_request_resources()
390 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", in stm32_gpio_irq_request_resources()
391 irq_data->hwirq); in stm32_gpio_irq_request_resources()
400 struct stm32_gpio_bank *bank = irq_data->domain->host_data; in stm32_gpio_irq_release_resources()
402 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_release_resources()
428 if ((fwspec->param_count != 2) || in stm32_gpio_domain_translate()
429 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE)) in stm32_gpio_domain_translate()
430 return -EINVAL; in stm32_gpio_domain_translate()
432 *hwirq = fwspec->param[0]; in stm32_gpio_domain_translate()
433 *type = fwspec->param[1]; in stm32_gpio_domain_translate()
440 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_activate()
441 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_activate()
444 if (pctl->hwlock) { in stm32_gpio_domain_activate()
445 ret = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_gpio_domain_activate()
448 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_gpio_domain_activate()
453 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); in stm32_gpio_domain_activate()
455 if (pctl->hwlock) in stm32_gpio_domain_activate()
456 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_gpio_domain_activate()
465 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_alloc()
468 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_alloc()
469 irq_hw_number_t hwirq = fwspec->param[0]; in stm32_gpio_domain_alloc()
474 * Check first that the IRQ MUX of that line is free. in stm32_gpio_domain_alloc()
475 * gpio irq mux is shared between several banks, protect with a lock in stm32_gpio_domain_alloc()
477 spin_lock_irqsave(&pctl->irqmux_lock, flags); in stm32_gpio_domain_alloc()
479 if (pctl->irqmux_map & BIT(hwirq)) { in stm32_gpio_domain_alloc()
480 dev_err(pctl->dev, "irq line %ld already requested.\n", hwirq); in stm32_gpio_domain_alloc()
481 ret = -EBUSY; in stm32_gpio_domain_alloc()
483 pctl->irqmux_map |= BIT(hwirq); in stm32_gpio_domain_alloc()
486 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); in stm32_gpio_domain_alloc()
490 parent_fwspec.fwnode = d->parent->fwnode; in stm32_gpio_domain_alloc()
492 parent_fwspec.param[0] = fwspec->param[0]; in stm32_gpio_domain_alloc()
493 parent_fwspec.param[1] = fwspec->param[1]; in stm32_gpio_domain_alloc()
504 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_free()
505 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_free()
507 unsigned long flags, hwirq = irq_data->hwirq; in stm32_gpio_domain_free()
511 spin_lock_irqsave(&pctl->irqmux_lock, flags); in stm32_gpio_domain_free()
512 pctl->irqmux_map &= ~BIT(hwirq); in stm32_gpio_domain_free()
513 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); in stm32_gpio_domain_free()
529 for (i = 0; i < pctl->ngroups; i++) { in stm32_pctrl_find_group_by_pin()
530 struct stm32_pinctrl_group *grp = pctl->groups + i; in stm32_pctrl_find_group_by_pin()
532 if (grp->pin == pin) in stm32_pctrl_find_group_by_pin()
544 for (i = 0; i < pctl->npins; i++) { in stm32_pctrl_is_function_valid()
545 const struct stm32_desc_pin *pin = pctl->pins + i; in stm32_pctrl_is_function_valid()
546 const struct stm32_desc_function *func = pin->functions; in stm32_pctrl_is_function_valid()
548 if (pin->pin.number != pin_num) in stm32_pctrl_is_function_valid()
552 if (func->num == fnum) in stm32_pctrl_is_function_valid()
560 dev_err(pctl->dev, "invalid function %d on pin %d .\n", fnum, pin_num); in stm32_pctrl_is_function_valid()
571 return -ENOSPC; in stm32_pctrl_dt_node_to_map_func()
574 (*map)[*num_maps].data.mux.group = grp->name; in stm32_pctrl_dt_node_to_map_func()
577 return -EINVAL; in stm32_pctrl_dt_node_to_map_func()
605 dev_err(pctl->dev, "missing pins property in node %pOFn .\n", in stm32_pctrl_dt_subnode_to_map()
607 return -EINVAL; in stm32_pctrl_dt_subnode_to_map()
618 num_pins = pins->length / sizeof(u32); in stm32_pctrl_dt_subnode_to_map()
627 err = -EINVAL; in stm32_pctrl_dt_subnode_to_map()
648 err = -EINVAL; in stm32_pctrl_dt_subnode_to_map()
654 dev_err(pctl->dev, "unable to match pin %d to group\n", in stm32_pctrl_dt_subnode_to_map()
656 err = -EINVAL; in stm32_pctrl_dt_subnode_to_map()
667 reserved_maps, num_maps, grp->name, in stm32_pctrl_dt_subnode_to_map()
709 return pctl->ngroups; in stm32_pctrl_get_groups_count()
717 return pctl->groups[group].name; in stm32_pctrl_get_group_name()
727 *pins = (unsigned *)&pctl->groups[group].pin; in stm32_pctrl_get_group_pins()
762 *groups = pctl->grp_names; in stm32_pmx_get_func_groups()
763 *num_groups = pctl->ngroups; in stm32_pmx_get_func_groups()
771 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pmx_set_mode()
778 spin_lock_irqsave(&bank->lock, flags); in stm32_pmx_set_mode()
780 if (pctl->hwlock) { in stm32_pmx_set_mode()
781 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_pmx_set_mode()
784 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_pmx_set_mode()
789 val = readl_relaxed(bank->base + alt_offset); in stm32_pmx_set_mode()
792 writel_relaxed(val, bank->base + alt_offset); in stm32_pmx_set_mode()
794 val = readl_relaxed(bank->base + STM32_GPIO_MODER); in stm32_pmx_set_mode()
797 writel_relaxed(val, bank->base + STM32_GPIO_MODER); in stm32_pmx_set_mode()
799 if (pctl->hwlock) in stm32_pmx_set_mode()
800 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_pmx_set_mode()
805 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pmx_set_mode()
818 spin_lock_irqsave(&bank->lock, flags); in stm32_pmx_get_mode()
820 val = readl_relaxed(bank->base + alt_offset); in stm32_pmx_get_mode()
824 val = readl_relaxed(bank->base + STM32_GPIO_MODER); in stm32_pmx_get_mode()
828 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pmx_get_mode()
837 struct stm32_pinctrl_group *g = pctl->groups + group; in stm32_pmx_set_mux()
843 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); in stm32_pmx_set_mux()
845 return -EINVAL; in stm32_pmx_set_mux()
847 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); in stm32_pmx_set_mux()
849 dev_err(pctl->dev, "No gpio range defined.\n"); in stm32_pmx_set_mux()
850 return -EINVAL; in stm32_pmx_set_mux()
853 bank = gpiochip_get_data(range->gc); in stm32_pmx_set_mux()
854 pin = stm32_gpio_pin(g->pin); in stm32_pmx_set_mux()
866 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); in stm32_pmx_gpio_set_direction()
879 dev_err(pctl->dev, "No gpio range defined.\n"); in stm32_pmx_request()
880 return -EINVAL; in stm32_pmx_request()
883 if (!gpiochip_line_is_valid(range->gc, stm32_gpio_pin(gpio))) { in stm32_pmx_request()
884 dev_warn(pctl->dev, "Can't access gpio %d\n", gpio); in stm32_pmx_request()
885 return -EACCES; in stm32_pmx_request()
906 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_driving()
911 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_driving()
913 if (pctl->hwlock) { in stm32_pconf_set_driving()
914 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_pconf_set_driving()
917 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_pconf_set_driving()
922 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); in stm32_pconf_set_driving()
925 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); in stm32_pconf_set_driving()
927 if (pctl->hwlock) in stm32_pconf_set_driving()
928 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_pconf_set_driving()
933 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_driving()
944 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_driving()
946 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); in stm32_pconf_get_driving()
949 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_driving()
957 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_speed()
962 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_speed()
964 if (pctl->hwlock) { in stm32_pconf_set_speed()
965 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_pconf_set_speed()
968 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_pconf_set_speed()
973 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_set_speed()
976 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_set_speed()
978 if (pctl->hwlock) in stm32_pconf_set_speed()
979 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_pconf_set_speed()
984 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_speed()
995 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_speed()
997 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_get_speed()
1000 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_speed()
1008 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_bias()
1013 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_bias()
1015 if (pctl->hwlock) { in stm32_pconf_set_bias()
1016 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_pconf_set_bias()
1019 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_pconf_set_bias()
1024 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); in stm32_pconf_set_bias()
1027 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); in stm32_pconf_set_bias()
1029 if (pctl->hwlock) in stm32_pconf_set_bias()
1030 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_pconf_set_bias()
1035 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_bias()
1046 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_bias()
1048 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); in stm32_pconf_get_bias()
1051 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_bias()
1062 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get()
1065 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & in stm32_pconf_get()
1068 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & in stm32_pconf_get()
1071 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get()
1087 dev_err(pctl->dev, "No gpio range defined.\n"); in stm32_pconf_parse_conf()
1088 return -EINVAL; in stm32_pconf_parse_conf()
1091 bank = gpiochip_get_data(range->gc); in stm32_pconf_parse_conf()
1094 if (!gpiochip_line_is_valid(range->gc, offset)) { in stm32_pconf_parse_conf()
1095 dev_warn(pctl->dev, "Can't access gpio %d\n", pin); in stm32_pconf_parse_conf()
1096 return -EACCES; in stm32_pconf_parse_conf()
1123 ret = -ENOTSUPP; in stm32_pconf_parse_conf()
1135 *config = pctl->groups[group].config; in stm32_pconf_group_get()
1144 struct stm32_pinctrl_group *g = &pctl->groups[group]; in stm32_pconf_group_set()
1148 mutex_lock(&pctldev->mutex); in stm32_pconf_group_set()
1149 ret = stm32_pconf_parse_conf(pctldev, g->pin, in stm32_pconf_group_set()
1152 mutex_unlock(&pctldev->mutex); in stm32_pconf_group_set()
1156 g->config = configs[i]; in stm32_pconf_group_set()
1182 struct stm32_desc_pin *pins = pctl->pins; in stm32_pconf_get_pin_desc_by_pin_number()
1185 for (i = 0; i < pctl->npins; i++) { in stm32_pconf_get_pin_desc_by_pin_number()
1186 if (pins->pin.number == pin_number) in stm32_pconf_get_pin_desc_by_pin_number()
1215 bank = gpiochip_get_data(range->gc); in stm32_pconf_dbg_show()
1218 if (!gpiochip_line_is_valid(range->gc, offset)) { in stm32_pconf_dbg_show()
1232 seq_printf(s, "- %s - %s", in stm32_pconf_dbg_show()
1242 seq_printf(s, "- %s - %s - %s - %s %s", in stm32_pconf_dbg_show()
1257 seq_printf(s, "%d (%s) - %s - %s - %s %s", alt, in stm32_pconf_dbg_show()
1258 pin_desc->functions[alt + 1].name, in stm32_pconf_dbg_show()
1281 unsigned int stm32_pin_nb = bank->bank_nr * STM32_GPIO_PINS_PER_BANK + offset; in stm32_pctrl_get_desc_pin_from_gpio()
1286 pin_desc = pctl->pins + stm32_pin_nb; in stm32_pctrl_get_desc_pin_from_gpio()
1287 if (pin_desc->pin.number == stm32_pin_nb) in stm32_pctrl_get_desc_pin_from_gpio()
1291 for (i = 0; i < pctl->npins; i++) { in stm32_pctrl_get_desc_pin_from_gpio()
1292 pin_desc = pctl->pins + i; in stm32_pctrl_get_desc_pin_from_gpio()
1293 if (pin_desc->pin.number == stm32_pin_nb) in stm32_pctrl_get_desc_pin_from_gpio()
1301 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; in stm32_gpiolib_register_bank()
1303 struct pinctrl_gpio_range *range = &bank->range; in stm32_gpiolib_register_bank()
1305 struct device *dev = pctl->dev; in stm32_gpiolib_register_bank()
1312 if (!IS_ERR(bank->rstc)) in stm32_gpiolib_register_bank()
1313 reset_control_deassert(bank->rstc); in stm32_gpiolib_register_bank()
1316 return -ENODEV; in stm32_gpiolib_register_bank()
1318 bank->base = devm_ioremap_resource(dev, &res); in stm32_gpiolib_register_bank()
1319 if (IS_ERR(bank->base)) in stm32_gpiolib_register_bank()
1320 return PTR_ERR(bank->base); in stm32_gpiolib_register_bank()
1322 err = clk_prepare_enable(bank->clk); in stm32_gpiolib_register_bank()
1328 bank->gpio_chip = stm32_gpio_template; in stm32_gpiolib_register_bank()
1330 fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label); in stm32_gpiolib_register_bank()
1332 if (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, i, &args)) { in stm32_gpiolib_register_bank()
1334 bank->gpio_chip.base = args.args[1]; in stm32_gpiolib_register_bank()
1338 while (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, ++i, &args)) in stm32_gpiolib_register_bank()
1341 bank_nr = pctl->nbanks; in stm32_gpiolib_register_bank()
1342 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1343 range->name = bank->gpio_chip.label; in stm32_gpiolib_register_bank()
1344 range->id = bank_nr; in stm32_gpiolib_register_bank()
1345 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1346 range->base = range->id * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1347 range->npins = npins; in stm32_gpiolib_register_bank()
1348 range->gc = &bank->gpio_chip; in stm32_gpiolib_register_bank()
1349 pinctrl_add_gpio_range(pctl->pctl_dev, in stm32_gpiolib_register_bank()
1350 &pctl->banks[bank_nr].range); in stm32_gpiolib_register_bank()
1353 if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr)) in stm32_gpiolib_register_bank()
1356 bank->gpio_chip.base = -1; in stm32_gpiolib_register_bank()
1358 bank->gpio_chip.ngpio = npins; in stm32_gpiolib_register_bank()
1359 bank->gpio_chip.fwnode = fwnode; in stm32_gpiolib_register_bank()
1360 bank->gpio_chip.parent = dev; in stm32_gpiolib_register_bank()
1361 bank->bank_nr = bank_nr; in stm32_gpiolib_register_bank()
1362 bank->bank_ioport_nr = bank_ioport_nr; in stm32_gpiolib_register_bank()
1363 bank->secure_control = pctl->match_data->secure_control; in stm32_gpiolib_register_bank()
1364 spin_lock_init(&bank->lock); in stm32_gpiolib_register_bank()
1366 if (pctl->domain) { in stm32_gpiolib_register_bank()
1367 /* create irq hierarchical domain */ in stm32_gpiolib_register_bank()
1368 bank->fwnode = fwnode; in stm32_gpiolib_register_bank()
1370 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE, in stm32_gpiolib_register_bank()
1371 bank->fwnode, &stm32_gpio_domain_ops, in stm32_gpiolib_register_bank()
1374 if (!bank->domain) { in stm32_gpiolib_register_bank()
1375 err = -ENODEV; in stm32_gpiolib_register_bank()
1383 if (stm32_pin && stm32_pin->pin.name) in stm32_gpiolib_register_bank()
1384 names[i] = devm_kasprintf(dev, GFP_KERNEL, "%s", stm32_pin->pin.name); in stm32_gpiolib_register_bank()
1389 bank->gpio_chip.names = (const char * const *)names; in stm32_gpiolib_register_bank()
1391 err = gpiochip_add_data(&bank->gpio_chip, bank); in stm32_gpiolib_register_bank()
1397 dev_info(dev, "%s bank added\n", bank->gpio_chip.label); in stm32_gpiolib_register_bank()
1401 clk_disable_unprepare(bank->clk); in stm32_gpiolib_register_bank()
1407 struct device_node *np = pdev->dev.of_node; in stm32_pctrl_get_irq_domain()
1411 if (!of_property_present(np, "interrupt-parent")) in stm32_pctrl_get_irq_domain()
1416 return ERR_PTR(-ENXIO); in stm32_pctrl_get_irq_domain()
1422 return ERR_PTR(-EPROBE_DEFER); in stm32_pctrl_get_irq_domain()
1430 struct device_node *np = pdev->dev.of_node; in stm32_pctrl_dt_setup_irq()
1431 struct device *dev = &pdev->dev; in stm32_pctrl_dt_setup_irq()
1436 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); in stm32_pctrl_dt_setup_irq()
1437 if (IS_ERR(pctl->regmap)) in stm32_pctrl_dt_setup_irq()
1438 return PTR_ERR(pctl->regmap); in stm32_pctrl_dt_setup_irq()
1440 rm = pctl->regmap; in stm32_pctrl_dt_setup_irq()
1442 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset); in stm32_pctrl_dt_setup_irq()
1446 ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask); in stm32_pctrl_dt_setup_irq()
1457 mux.msb = mux.lsb + mask_width - 1; in stm32_pctrl_dt_setup_irq()
1462 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); in stm32_pctrl_dt_setup_irq()
1463 if (IS_ERR(pctl->irqmux[i])) in stm32_pctrl_dt_setup_irq()
1464 return PTR_ERR(pctl->irqmux[i]); in stm32_pctrl_dt_setup_irq()
1475 pctl->ngroups = pctl->npins; in stm32_pctrl_build_state()
1478 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, in stm32_pctrl_build_state()
1479 sizeof(*pctl->groups), GFP_KERNEL); in stm32_pctrl_build_state()
1480 if (!pctl->groups) in stm32_pctrl_build_state()
1481 return -ENOMEM; in stm32_pctrl_build_state()
1484 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, in stm32_pctrl_build_state()
1485 sizeof(*pctl->grp_names), GFP_KERNEL); in stm32_pctrl_build_state()
1486 if (!pctl->grp_names) in stm32_pctrl_build_state()
1487 return -ENOMEM; in stm32_pctrl_build_state()
1489 for (i = 0; i < pctl->npins; i++) { in stm32_pctrl_build_state()
1490 const struct stm32_desc_pin *pin = pctl->pins + i; in stm32_pctrl_build_state()
1491 struct stm32_pinctrl_group *group = pctl->groups + i; in stm32_pctrl_build_state()
1493 group->name = pin->pin.name; in stm32_pctrl_build_state()
1494 group->pin = pin->pin.number; in stm32_pctrl_build_state()
1495 pctl->grp_names[i] = pin->pin.name; in stm32_pctrl_build_state()
1507 for (i = 0; i < pctl->match_data->npins; i++) { in stm32_pctrl_create_pins_tab()
1508 p = pctl->match_data->pins + i; in stm32_pctrl_create_pins_tab()
1509 if (pctl->pkg && !(pctl->pkg & p->pkg)) in stm32_pctrl_create_pins_tab()
1511 pins->pin = p->pin; in stm32_pctrl_create_pins_tab()
1512 memcpy((struct stm32_desc_pin *)pins->functions, p->functions, in stm32_pctrl_create_pins_tab()
1518 pctl->npins = nb_pins_available; in stm32_pctrl_create_pins_tab()
1527 struct device *dev = &pdev->dev; in stm32_pctl_probe()
1535 return -EINVAL; in stm32_pctl_probe()
1539 return -ENOMEM; in stm32_pctl_probe()
1543 /* check for IRQ controller (may require deferred probe) */ in stm32_pctl_probe()
1544 pctl->domain = stm32_pctrl_get_irq_domain(pdev); in stm32_pctl_probe()
1545 if (IS_ERR(pctl->domain)) in stm32_pctl_probe()
1546 return PTR_ERR(pctl->domain); in stm32_pctl_probe()
1547 if (!pctl->domain) in stm32_pctl_probe()
1551 hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0); in stm32_pctl_probe()
1553 if (hwlock_id == -EPROBE_DEFER) in stm32_pctl_probe()
1556 pctl->hwlock = hwspin_lock_request_specific(hwlock_id); in stm32_pctl_probe()
1559 spin_lock_init(&pctl->irqmux_lock); in stm32_pctl_probe()
1561 pctl->dev = dev; in stm32_pctl_probe()
1562 pctl->match_data = match_data; in stm32_pctl_probe()
1565 if (!device_property_read_u32(dev, "st,package", &pctl->pkg)) in stm32_pctl_probe()
1566 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg); in stm32_pctl_probe()
1568 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins, in stm32_pctl_probe()
1569 sizeof(*pctl->pins), GFP_KERNEL); in stm32_pctl_probe()
1570 if (!pctl->pins) in stm32_pctl_probe()
1571 return -ENOMEM; in stm32_pctl_probe()
1573 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins); in stm32_pctl_probe()
1580 return -EINVAL; in stm32_pctl_probe()
1583 if (pctl->domain) { in stm32_pctl_probe()
1589 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins), in stm32_pctl_probe()
1592 return -ENOMEM; in stm32_pctl_probe()
1594 for (i = 0; i < pctl->npins; i++) in stm32_pctl_probe()
1595 pins[i] = pctl->pins[i].pin; in stm32_pctl_probe()
1597 pctl->pctl_desc.name = dev_name(&pdev->dev); in stm32_pctl_probe()
1598 pctl->pctl_desc.owner = THIS_MODULE; in stm32_pctl_probe()
1599 pctl->pctl_desc.pins = pins; in stm32_pctl_probe()
1600 pctl->pctl_desc.npins = pctl->npins; in stm32_pctl_probe()
1601 pctl->pctl_desc.link_consumers = true; in stm32_pctl_probe()
1602 pctl->pctl_desc.confops = &stm32_pconf_ops; in stm32_pctl_probe()
1603 pctl->pctl_desc.pctlops = &stm32_pctrl_ops; in stm32_pctl_probe()
1604 pctl->pctl_desc.pmxops = &stm32_pmx_ops; in stm32_pctl_probe()
1605 pctl->dev = &pdev->dev; in stm32_pctl_probe()
1607 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, in stm32_pctl_probe()
1610 if (IS_ERR(pctl->pctl_dev)) { in stm32_pctl_probe()
1611 dev_err(&pdev->dev, "Failed pinctrl registration\n"); in stm32_pctl_probe()
1612 return PTR_ERR(pctl->pctl_dev); in stm32_pctl_probe()
1618 return -EINVAL; in stm32_pctl_probe()
1620 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), in stm32_pctl_probe()
1622 if (!pctl->banks) in stm32_pctl_probe()
1623 return -ENOMEM; in stm32_pctl_probe()
1627 struct stm32_gpio_bank *bank = &pctl->banks[i]; in stm32_pctl_probe()
1630 bank->rstc = of_reset_control_get_exclusive(np, NULL); in stm32_pctl_probe()
1631 if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) { in stm32_pctl_probe()
1633 return -EPROBE_DEFER; in stm32_pctl_probe()
1636 bank->clk = of_clk_get_by_name(np, NULL); in stm32_pctl_probe()
1637 if (IS_ERR(bank->clk)) { in stm32_pctl_probe()
1639 return dev_err_probe(dev, PTR_ERR(bank->clk), in stm32_pctl_probe()
1650 for (i = 0; i < pctl->nbanks; i++) in stm32_pctl_probe()
1651 clk_disable_unprepare(pctl->banks[i].clk); in stm32_pctl_probe()
1656 pctl->nbanks++; in stm32_pctl_probe()
1667 const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin); in stm32_pinctrl_restore_gpio_regs()
1674 range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin); in stm32_pinctrl_restore_gpio_regs()
1678 if (!gpiochip_line_is_valid(range->gc, offset)) in stm32_pinctrl_restore_gpio_regs()
1681 pin_is_irq = gpiochip_line_is_irq(range->gc, offset); in stm32_pinctrl_restore_gpio_regs()
1683 if (!desc || (!pin_is_irq && !desc->gpio_owner)) in stm32_pinctrl_restore_gpio_regs()
1686 bank = gpiochip_get_data(range->gc); in stm32_pinctrl_restore_gpio_regs()
1688 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK; in stm32_pinctrl_restore_gpio_regs()
1690 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK; in stm32_pinctrl_restore_gpio_regs()
1698 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL); in stm32_pinctrl_restore_gpio_regs()
1703 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE); in stm32_pinctrl_restore_gpio_regs()
1709 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK; in stm32_pinctrl_restore_gpio_regs()
1715 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK; in stm32_pinctrl_restore_gpio_regs()
1722 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr); in stm32_pinctrl_restore_gpio_regs()
1732 for (i = 0; i < pctl->nbanks; i++) in stm32_pinctrl_suspend()
1733 clk_disable(pctl->banks[i].clk); in stm32_pinctrl_suspend()
1741 struct stm32_pinctrl_group *g = pctl->groups; in stm32_pinctrl_resume()
1744 for (i = 0; i < pctl->nbanks; i++) in stm32_pinctrl_resume()
1745 clk_enable(pctl->banks[i].clk); in stm32_pinctrl_resume()
1747 for (i = 0; i < pctl->ngroups; i++, g++) in stm32_pinctrl_resume()
1748 stm32_pinctrl_restore_gpio_regs(pctl, g->pin); in stm32_pinctrl_resume()