Lines Matching +full:gpi +full:- +full:config
1 // SPDX-License-Identifier: GPL-2.0
27 #include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
30 #include "../pinctrl-utils.h"
33 #include "pinctrl-starfive-jh7110.h"
52 * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 |
100 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_pin_dbg_show()
102 seq_printf(s, "%s", dev_name(pctldev->dev)); in jh7110_pin_dbg_show()
104 if (pin < sfp->gc.ngpio) { in jh7110_pin_dbg_show()
107 u32 dout = readl_relaxed(sfp->base + info->dout_reg_base + offset); in jh7110_pin_dbg_show()
108 u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset); in jh7110_pin_dbg_show()
109 u32 gpi = readl_relaxed(sfp->base + info->gpi_reg_base + offset); in jh7110_pin_dbg_show() local
111 dout = (dout >> shift) & info->dout_mask; in jh7110_pin_dbg_show()
112 doen = (doen >> shift) & info->doen_mask; in jh7110_pin_dbg_show()
113 gpi = ((gpi >> shift) - 2) & info->gpi_mask; in jh7110_pin_dbg_show()
115 seq_printf(s, " dout=%u doen=%u din=%u", dout, doen, gpi); in jh7110_pin_dbg_show()
128 struct device *dev = sfp->gc.parent; in jh7110_dt_node_to_map()
144 return -ENOMEM; in jh7110_dt_node_to_map()
148 return -ENOMEM; in jh7110_dt_node_to_map()
152 mutex_lock(&sfp->mutex); in jh7110_dt_node_to_map()
163 ret = -EINVAL; in jh7110_dt_node_to_map()
169 ret = -ENOMEM; in jh7110_dt_node_to_map()
177 ret = -ENOMEM; in jh7110_dt_node_to_map()
183 ret = -ENOMEM; in jh7110_dt_node_to_map()
195 map[nmaps].data.mux.function = np->name; in jh7110_dt_node_to_map()
210 dev_err(dev, "error parsing pin config of group %s: %d\n", in jh7110_dt_node_to_map()
224 ret = pinmux_generic_add_function(pctldev, np->name, in jh7110_dt_node_to_map()
227 dev_err(dev, "error adding function %s: %d\n", np->name, ret); in jh7110_dt_node_to_map()
230 mutex_unlock(&sfp->mutex); in jh7110_dt_node_to_map()
240 mutex_unlock(&sfp->mutex); in jh7110_dt_node_to_map()
256 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_set_gpiomux()
260 u32 dout_mask = info->dout_mask << shift; in jh7110_set_gpiomux()
261 u32 done_mask = info->doen_mask << shift; in jh7110_set_gpiomux()
268 reg_dout = sfp->base + info->dout_reg_base + offset; in jh7110_set_gpiomux()
269 reg_doen = sfp->base + info->doen_reg_base + offset; in jh7110_set_gpiomux()
276 reg_din = sfp->base + info->gpi_reg_base + ioffset; in jh7110_set_gpiomux()
278 imask = info->gpi_mask << ishift; in jh7110_set_gpiomux()
283 raw_spin_lock_irqsave(&sfp->lock, flags); in jh7110_set_gpiomux()
292 raw_spin_unlock_irqrestore(&sfp->lock, flags); in jh7110_set_gpiomux()
300 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_set_mux()
307 return -EINVAL; in jh7110_set_mux()
309 pinmux = group->data; in jh7110_set_mux()
310 for (i = 0; i < group->num_pins; i++) { in jh7110_set_mux()
313 if (info->jh7110_set_one_pin_mux) in jh7110_set_mux()
314 info->jh7110_set_one_pin_mux(sfp, in jh7110_set_mux()
354 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_padcfg_rmw()
359 if (!info->jh7110_get_padcfg_base) in jh7110_padcfg_rmw()
362 padcfg_base = info->jh7110_get_padcfg_base(sfp, pin); in jh7110_padcfg_rmw()
366 reg = sfp->base + padcfg_base + 4 * pin; in jh7110_padcfg_rmw()
369 raw_spin_lock_irqsave(&sfp->lock, flags); in jh7110_padcfg_rmw()
372 raw_spin_unlock_irqrestore(&sfp->lock, flags); in jh7110_padcfg_rmw()
376 unsigned int pin, unsigned long *config) in jh7110_pinconf_get() argument
379 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_pinconf_get()
380 int param = pinconf_to_config_param(*config); in jh7110_pinconf_get()
385 if (!info->jh7110_get_padcfg_base) in jh7110_pinconf_get()
388 padcfg_base = info->jh7110_get_padcfg_base(sfp, pin); in jh7110_pinconf_get()
392 padcfg = readl_relaxed(sfp->base + padcfg_base + 4 * pin); in jh7110_pinconf_get()
423 return -ENOTSUPP; in jh7110_pinconf_get()
426 *config = pinconf_to_config_packed(param, arg); in jh7110_pinconf_get()
427 return enabled ? 0 : -EINVAL; in jh7110_pinconf_get()
432 unsigned long *config) in jh7110_pinconf_group_get() argument
438 return -EINVAL; in jh7110_pinconf_group_get()
440 return jh7110_pinconf_get(pctldev, group->pins[0], config); in jh7110_pinconf_group_get()
455 return -EINVAL; in jh7110_pinconf_group_set()
470 return -ENOTSUPP; in jh7110_pinconf_group_set()
476 return -ENOTSUPP; in jh7110_pinconf_group_set()
507 return -ENOTSUPP; in jh7110_pinconf_group_set()
511 for (i = 0; i < group->num_pins; i++) in jh7110_pinconf_group_set()
512 jh7110_padcfg_rmw(sfp, group->pins[i], mask, value); in jh7110_pinconf_group_set()
522 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_pinconf_dbg_show()
526 if (!info->jh7110_get_padcfg_base) in jh7110_pinconf_dbg_show()
529 padcfg_base = info->jh7110_get_padcfg_base(sfp, pin); in jh7110_pinconf_dbg_show()
533 value = readl_relaxed(sfp->base + padcfg_base + 4 * pin); in jh7110_pinconf_dbg_show()
550 return pinctrl_gpio_request(gc->base + gpio); in jh7110_gpio_request()
555 pinctrl_gpio_free(gc->base + gpio); in jh7110_gpio_free()
563 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_gpio_get_direction()
566 u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset); in jh7110_gpio_get_direction()
568 doen = (doen >> shift) & info->doen_mask; in jh7110_gpio_get_direction()
579 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_gpio_direction_input()
586 if (info->jh7110_set_one_pin_mux) in jh7110_gpio_direction_input()
587 info->jh7110_set_one_pin_mux(sfp, gpio, in jh7110_gpio_direction_input()
598 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_gpio_direction_output()
600 if (info->jh7110_set_one_pin_mux) in jh7110_gpio_direction_output()
601 info->jh7110_set_one_pin_mux(sfp, gpio, in jh7110_gpio_direction_output()
616 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_gpio_get()
617 void __iomem *reg = sfp->base + info->gpioin_reg_base in jh7110_gpio_get()
628 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_gpio_set()
631 void __iomem *reg_dout = sfp->base + info->dout_reg_base + offset; in jh7110_gpio_set()
633 u32 mask = info->dout_mask << shift; in jh7110_gpio_set()
636 raw_spin_lock_irqsave(&sfp->lock, flags); in jh7110_gpio_set()
639 raw_spin_unlock_irqrestore(&sfp->lock, flags); in jh7110_gpio_set()
643 unsigned int gpio, unsigned long config) in jh7110_gpio_set_config() argument
647 u32 arg = pinconf_to_config_argument(config); in jh7110_gpio_set_config()
651 switch (pinconf_to_config_param(config)) { in jh7110_gpio_set_config()
658 return -ENOTSUPP; in jh7110_gpio_set_config()
664 return -ENOTSUPP; in jh7110_gpio_set_config()
679 return -ENOTSUPP; in jh7110_gpio_set_config()
691 sfp->gpios.name = sfp->gc.label; in jh7110_gpio_add_pin_ranges()
692 sfp->gpios.base = sfp->gc.base; in jh7110_gpio_add_pin_ranges()
693 sfp->gpios.pin_base = 0; in jh7110_gpio_add_pin_ranges()
694 sfp->gpios.npins = sfp->gc.ngpio; in jh7110_gpio_add_pin_ranges()
695 sfp->gpios.gc = &sfp->gc; in jh7110_gpio_add_pin_ranges()
696 pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios); in jh7110_gpio_add_pin_ranges()
703 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg; in jh7110_irq_ack()
705 void __iomem *ic = sfp->base + irq_reg->ic_reg_base in jh7110_irq_ack()
711 raw_spin_lock_irqsave(&sfp->lock, flags); in jh7110_irq_ack()
715 raw_spin_unlock_irqrestore(&sfp->lock, flags); in jh7110_irq_ack()
721 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg; in jh7110_irq_mask()
723 void __iomem *ie = sfp->base + irq_reg->ie_reg_base in jh7110_irq_mask()
729 raw_spin_lock_irqsave(&sfp->lock, flags); in jh7110_irq_mask()
732 raw_spin_unlock_irqrestore(&sfp->lock, flags); in jh7110_irq_mask()
734 gpiochip_disable_irq(&sfp->gc, d->hwirq); in jh7110_irq_mask()
740 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg; in jh7110_irq_mask_ack()
742 void __iomem *ie = sfp->base + irq_reg->ie_reg_base in jh7110_irq_mask_ack()
744 void __iomem *ic = sfp->base + irq_reg->ic_reg_base in jh7110_irq_mask_ack()
750 raw_spin_lock_irqsave(&sfp->lock, flags); in jh7110_irq_mask_ack()
757 raw_spin_unlock_irqrestore(&sfp->lock, flags); in jh7110_irq_mask_ack()
763 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg; in jh7110_irq_unmask()
765 void __iomem *ie = sfp->base + irq_reg->ie_reg_base in jh7110_irq_unmask()
771 gpiochip_enable_irq(&sfp->gc, d->hwirq); in jh7110_irq_unmask()
773 raw_spin_lock_irqsave(&sfp->lock, flags); in jh7110_irq_unmask()
776 raw_spin_unlock_irqrestore(&sfp->lock, flags); in jh7110_irq_unmask()
782 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg; in jh7110_irq_set_type()
784 void __iomem *base = sfp->base + 4 * (gpio / 32); in jh7110_irq_set_type()
816 return -EINVAL; in jh7110_irq_set_type()
824 raw_spin_lock_irqsave(&sfp->lock, flags); in jh7110_irq_set_type()
825 irq_type |= readl_relaxed(base + irq_reg->is_reg_base) & ~mask; in jh7110_irq_set_type()
826 writel_relaxed(irq_type, base + irq_reg->is_reg_base); in jh7110_irq_set_type()
828 edge_both |= readl_relaxed(base + irq_reg->ibe_reg_base) & ~mask; in jh7110_irq_set_type()
829 writel_relaxed(edge_both, base + irq_reg->ibe_reg_base); in jh7110_irq_set_type()
831 polarity |= readl_relaxed(base + irq_reg->iev_reg_base) & ~mask; in jh7110_irq_set_type()
832 writel_relaxed(polarity, base + irq_reg->iev_reg_base); in jh7110_irq_set_type()
833 raw_spin_unlock_irqrestore(&sfp->lock, flags); in jh7110_irq_set_type()
854 struct device *dev = &pdev->dev; in jh7110_pinctrl_probe()
862 info = of_device_get_match_data(&pdev->dev); in jh7110_pinctrl_probe()
864 return -ENODEV; in jh7110_pinctrl_probe()
866 if (!info->pins || !info->npins) { in jh7110_pinctrl_probe()
868 return -EINVAL; in jh7110_pinctrl_probe()
873 return -ENOMEM; in jh7110_pinctrl_probe()
876 sfp->saved_regs = devm_kcalloc(dev, info->nsaved_regs, in jh7110_pinctrl_probe()
877 sizeof(*sfp->saved_regs), GFP_KERNEL); in jh7110_pinctrl_probe()
878 if (!sfp->saved_regs) in jh7110_pinctrl_probe()
879 return -ENOMEM; in jh7110_pinctrl_probe()
882 sfp->base = devm_platform_ioremap_resource(pdev, 0); in jh7110_pinctrl_probe()
883 if (IS_ERR(sfp->base)) in jh7110_pinctrl_probe()
884 return PTR_ERR(sfp->base); in jh7110_pinctrl_probe()
913 jh7110_pinctrl_desc = devm_kzalloc(&pdev->dev, in jh7110_pinctrl_probe()
917 return -ENOMEM; in jh7110_pinctrl_probe()
919 jh7110_pinctrl_desc->name = dev_name(dev); in jh7110_pinctrl_probe()
920 jh7110_pinctrl_desc->pins = info->pins; in jh7110_pinctrl_probe()
921 jh7110_pinctrl_desc->npins = info->npins; in jh7110_pinctrl_probe()
922 jh7110_pinctrl_desc->pctlops = &jh7110_pinctrl_ops; in jh7110_pinctrl_probe()
923 jh7110_pinctrl_desc->pmxops = &jh7110_pinmux_ops; in jh7110_pinctrl_probe()
924 jh7110_pinctrl_desc->confops = &jh7110_pinconf_ops; in jh7110_pinctrl_probe()
925 jh7110_pinctrl_desc->owner = THIS_MODULE; in jh7110_pinctrl_probe()
927 sfp->info = info; in jh7110_pinctrl_probe()
928 sfp->dev = dev; in jh7110_pinctrl_probe()
930 sfp->gc.parent = dev; in jh7110_pinctrl_probe()
931 raw_spin_lock_init(&sfp->lock); in jh7110_pinctrl_probe()
932 mutex_init(&sfp->mutex); in jh7110_pinctrl_probe()
936 sfp, &sfp->pctl); in jh7110_pinctrl_probe()
941 sfp->gc.label = dev_name(dev); in jh7110_pinctrl_probe()
942 sfp->gc.owner = THIS_MODULE; in jh7110_pinctrl_probe()
943 sfp->gc.request = jh7110_gpio_request; in jh7110_pinctrl_probe()
944 sfp->gc.free = jh7110_gpio_free; in jh7110_pinctrl_probe()
945 sfp->gc.get_direction = jh7110_gpio_get_direction; in jh7110_pinctrl_probe()
946 sfp->gc.direction_input = jh7110_gpio_direction_input; in jh7110_pinctrl_probe()
947 sfp->gc.direction_output = jh7110_gpio_direction_output; in jh7110_pinctrl_probe()
948 sfp->gc.get = jh7110_gpio_get; in jh7110_pinctrl_probe()
949 sfp->gc.set = jh7110_gpio_set; in jh7110_pinctrl_probe()
950 sfp->gc.set_config = jh7110_gpio_set_config; in jh7110_pinctrl_probe()
951 sfp->gc.add_pin_ranges = jh7110_gpio_add_pin_ranges; in jh7110_pinctrl_probe()
952 sfp->gc.base = info->gc_base; in jh7110_pinctrl_probe()
953 sfp->gc.ngpio = info->ngpios; in jh7110_pinctrl_probe()
955 jh7110_irq_chip.name = sfp->gc.label; in jh7110_pinctrl_probe()
956 gpio_irq_chip_set_chip(&sfp->gc.irq, &jh7110_irq_chip); in jh7110_pinctrl_probe()
957 sfp->gc.irq.parent_handler = info->jh7110_gpio_irq_handler; in jh7110_pinctrl_probe()
958 sfp->gc.irq.num_parents = 1; in jh7110_pinctrl_probe()
959 sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents, in jh7110_pinctrl_probe()
960 sizeof(*sfp->gc.irq.parents), in jh7110_pinctrl_probe()
962 if (!sfp->gc.irq.parents) in jh7110_pinctrl_probe()
963 return -ENOMEM; in jh7110_pinctrl_probe()
964 sfp->gc.irq.default_type = IRQ_TYPE_NONE; in jh7110_pinctrl_probe()
965 sfp->gc.irq.handler = handle_bad_irq; in jh7110_pinctrl_probe()
966 sfp->gc.irq.init_hw = info->jh7110_gpio_init_hw; in jh7110_pinctrl_probe()
971 sfp->gc.irq.parents[0] = ret; in jh7110_pinctrl_probe()
973 ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp); in jh7110_pinctrl_probe()
977 dev_info(dev, "StarFive GPIO chip registered %d GPIOs\n", sfp->gc.ngpio); in jh7110_pinctrl_probe()
979 return pinctrl_enable(sfp->pctl); in jh7110_pinctrl_probe()
989 raw_spin_lock_irqsave(&sfp->lock, flags); in jh7110_pinctrl_suspend()
990 for (i = 0 ; i < sfp->info->nsaved_regs ; i++) in jh7110_pinctrl_suspend()
991 sfp->saved_regs[i] = readl_relaxed(sfp->base + 4 * i); in jh7110_pinctrl_suspend()
993 raw_spin_unlock_irqrestore(&sfp->lock, flags); in jh7110_pinctrl_suspend()
1003 raw_spin_lock_irqsave(&sfp->lock, flags); in jh7110_pinctrl_resume()
1004 for (i = 0 ; i < sfp->info->nsaved_regs ; i++) in jh7110_pinctrl_resume()
1005 writel_relaxed(sfp->saved_regs[i], sfp->base + 4 * i); in jh7110_pinctrl_resume()
1007 raw_spin_unlock_irqrestore(&sfp->lock, flags); in jh7110_pinctrl_resume()