Lines Matching refs:pctrl
163 static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, in rzg2l_pinctrl_set_pfc_mode() argument
169 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_pinctrl_set_pfc_mode()
172 reg = readw(pctrl->base + PM(port)); in rzg2l_pinctrl_set_pfc_mode()
174 writew(reg, pctrl->base + PM(port)); in rzg2l_pinctrl_set_pfc_mode()
177 reg = readb(pctrl->base + PMC(port)); in rzg2l_pinctrl_set_pfc_mode()
178 writeb(reg & ~BIT(pin), pctrl->base + PMC(port)); in rzg2l_pinctrl_set_pfc_mode()
181 writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ in rzg2l_pinctrl_set_pfc_mode()
182 writel(PWPR_PFCWE, pctrl->base + PWPR); /* B0WI=0, PFCWE=1 */ in rzg2l_pinctrl_set_pfc_mode()
185 reg = readl(pctrl->base + PFC(port)); in rzg2l_pinctrl_set_pfc_mode()
187 writel(reg | (func << (pin * 4)), pctrl->base + PFC(port)); in rzg2l_pinctrl_set_pfc_mode()
190 writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ in rzg2l_pinctrl_set_pfc_mode()
191 writel(PWPR_B0WI, pctrl->base + PWPR); /* B0WI=1, PFCWE=0 */ in rzg2l_pinctrl_set_pfc_mode()
194 reg = readb(pctrl->base + PMC(port)); in rzg2l_pinctrl_set_pfc_mode()
195 writeb(reg | BIT(pin), pctrl->base + PMC(port)); in rzg2l_pinctrl_set_pfc_mode()
197 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_pinctrl_set_pfc_mode()
204 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_pinctrl_set_mux() local
221 dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n", in rzg2l_pinctrl_set_mux()
224 rzg2l_pinctrl_set_pfc_mode(pctrl, RZG2L_PIN_ID_TO_PORT(pins[i]), in rzg2l_pinctrl_set_mux()
259 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_dt_subnode_to_map() local
283 dev_err(pctrl->dev, "Invalid pins list in DT\n"); in rzg2l_dt_subnode_to_map()
293 dev_err(pctrl->dev, in rzg2l_dt_subnode_to_map()
303 dev_err(pctrl->dev, "DT node must contain a config\n"); in rzg2l_dt_subnode_to_map()
336 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); in rzg2l_dt_subnode_to_map()
337 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), in rzg2l_dt_subnode_to_map()
339 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); in rzg2l_dt_subnode_to_map()
357 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", in rzg2l_dt_subnode_to_map()
367 mutex_lock(&pctrl->mutex); in rzg2l_dt_subnode_to_map()
387 mutex_unlock(&pctrl->mutex); in rzg2l_dt_subnode_to_map()
394 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); in rzg2l_dt_subnode_to_map()
401 mutex_unlock(&pctrl->mutex); in rzg2l_dt_subnode_to_map()
430 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_dt_node_to_map() local
458 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); in rzg2l_dt_node_to_map()
467 static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, in rzg2l_validate_gpio_pin() argument
474 if (bit >= pincount || port >= pctrl->data->n_port_pins) in rzg2l_validate_gpio_pin()
477 data = pctrl->data->port_pin_configs[port]; in rzg2l_validate_gpio_pin()
484 static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, in rzg2l_read_pin_config() argument
487 void __iomem *addr = pctrl->base + offset; in rzg2l_read_pin_config()
498 static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, in rzg2l_rmw_pin_config() argument
501 void __iomem *addr = pctrl->base + offset; in rzg2l_rmw_pin_config()
511 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_rmw_pin_config()
514 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_rmw_pin_config()
521 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_pinctrl_pinconf_get() local
523 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; in rzg2l_pinctrl_pinconf_get()
544 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) in rzg2l_pinctrl_pinconf_get()
552 arg = rzg2l_read_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK); in rzg2l_pinctrl_pinconf_get()
569 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_pinctrl_pinconf_get()
570 addr = pctrl->base + pwr_reg; in rzg2l_pinctrl_pinconf_get()
572 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_pinctrl_pinconf_get()
582 index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK); in rzg2l_pinctrl_pinconf_get()
593 index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK); in rzg2l_pinctrl_pinconf_get()
612 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_pinctrl_pinconf_set() local
613 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; in rzg2l_pinctrl_pinconf_set()
635 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) in rzg2l_pinctrl_pinconf_set()
649 rzg2l_rmw_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK, !!arg); in rzg2l_pinctrl_pinconf_set()
669 addr = pctrl->base + pwr_reg; in rzg2l_pinctrl_pinconf_set()
670 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_pinctrl_pinconf_set()
672 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_pinctrl_pinconf_set()
690 rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index); in rzg2l_pinctrl_pinconf_set()
708 rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index); in rzg2l_pinctrl_pinconf_set()
797 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_request() local
808 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_request()
811 reg8 = readb(pctrl->base + PMC(port)); in rzg2l_gpio_request()
813 writeb(reg8, pctrl->base + PMC(port)); in rzg2l_gpio_request()
815 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_request()
820 static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 port, in rzg2l_gpio_set_direction() argument
826 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_set_direction()
828 reg16 = readw(pctrl->base + PM(port)); in rzg2l_gpio_set_direction()
832 writew(reg16, pctrl->base + PM(port)); in rzg2l_gpio_set_direction()
834 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_set_direction()
839 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_get_direction() local
843 if (!(readb(pctrl->base + PMC(port)) & BIT(bit))) { in rzg2l_gpio_get_direction()
846 reg16 = readw(pctrl->base + PM(port)); in rzg2l_gpio_get_direction()
858 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_direction_input() local
862 rzg2l_gpio_set_direction(pctrl, port, bit, false); in rzg2l_gpio_direction_input()
870 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_set() local
876 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_set()
878 reg8 = readb(pctrl->base + P(port)); in rzg2l_gpio_set()
881 writeb(reg8 | BIT(bit), pctrl->base + P(port)); in rzg2l_gpio_set()
883 writeb(reg8 & ~BIT(bit), pctrl->base + P(port)); in rzg2l_gpio_set()
885 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_set()
891 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_direction_output() local
896 rzg2l_gpio_set_direction(pctrl, port, bit, true); in rzg2l_gpio_direction_output()
903 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_get() local
908 reg16 = readw(pctrl->base + PM(port)); in rzg2l_gpio_get()
912 return !!(readb(pctrl->base + PIN(port)) & BIT(bit)); in rzg2l_gpio_get()
914 return !!(readb(pctrl->base + P(port)) & BIT(bit)); in rzg2l_gpio_get()
1171 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); in rzg2l_gpio_irq_disable() local
1181 addr = pctrl->base + ISEL(port); in rzg2l_gpio_irq_disable()
1187 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_irq_disable()
1189 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_irq_disable()
1198 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); in rzg2l_gpio_irq_enable() local
1210 addr = pctrl->base + ISEL(port); in rzg2l_gpio_irq_enable()
1216 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_irq_enable()
1218 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_irq_enable()
1259 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); in rzg2l_gpio_child_to_parent_hwirq() local
1263 gpioint = rzg2l_gpio_get_gpioint(child, pctrl->data); in rzg2l_gpio_child_to_parent_hwirq()
1267 spin_lock_irqsave(&pctrl->bitmap_lock, flags); in rzg2l_gpio_child_to_parent_hwirq()
1268 irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1)); in rzg2l_gpio_child_to_parent_hwirq()
1269 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); in rzg2l_gpio_child_to_parent_hwirq()
1272 pctrl->hwirq[irq] = child; in rzg2l_gpio_child_to_parent_hwirq()
1304 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); in rzg2l_gpio_irq_domain_free() local
1310 if (pctrl->hwirq[i] == hwirq) { in rzg2l_gpio_irq_domain_free()
1311 spin_lock_irqsave(&pctrl->bitmap_lock, flags); in rzg2l_gpio_irq_domain_free()
1312 bitmap_release_region(pctrl->tint_slot, i, get_order(1)); in rzg2l_gpio_irq_domain_free()
1313 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); in rzg2l_gpio_irq_domain_free()
1314 pctrl->hwirq[i] = 0; in rzg2l_gpio_irq_domain_free()
1326 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); in rzg2l_init_irq_valid_mask() local
1327 struct gpio_chip *chip = &pctrl->gpio_chip; in rzg2l_init_irq_valid_mask()
1337 if (port >= pctrl->data->n_ports || in rzg2l_init_irq_valid_mask()
1338 bit >= RZG2L_GPIO_PORT_GET_PINCNT(pctrl->data->port_pin_configs[port])) in rzg2l_init_irq_valid_mask()
1343 static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) in rzg2l_gpio_register() argument
1345 struct device_node *np = pctrl->dev->of_node; in rzg2l_gpio_register()
1346 struct gpio_chip *chip = &pctrl->gpio_chip; in rzg2l_gpio_register()
1347 const char *name = dev_name(pctrl->dev); in rzg2l_gpio_register()
1365 dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); in rzg2l_gpio_register()
1370 of_args.args[2] != pctrl->data->n_port_pins) { in rzg2l_gpio_register()
1371 dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n"); in rzg2l_gpio_register()
1375 chip->names = pctrl->data->port_pins; in rzg2l_gpio_register()
1384 chip->parent = pctrl->dev; in rzg2l_gpio_register()
1398 pctrl->gpio_range.id = 0; in rzg2l_gpio_register()
1399 pctrl->gpio_range.pin_base = 0; in rzg2l_gpio_register()
1400 pctrl->gpio_range.base = 0; in rzg2l_gpio_register()
1401 pctrl->gpio_range.npins = chip->ngpio; in rzg2l_gpio_register()
1402 pctrl->gpio_range.name = chip->label; in rzg2l_gpio_register()
1403 pctrl->gpio_range.gc = chip; in rzg2l_gpio_register()
1404 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); in rzg2l_gpio_register()
1406 dev_err(pctrl->dev, "failed to add GPIO controller\n"); in rzg2l_gpio_register()
1410 dev_dbg(pctrl->dev, "Registered gpio controller\n"); in rzg2l_gpio_register()
1415 static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) in rzg2l_pinctrl_register() argument
1422 pctrl->desc.name = DRV_NAME; in rzg2l_pinctrl_register()
1423 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; in rzg2l_pinctrl_register()
1424 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops; in rzg2l_pinctrl_register()
1425 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops; in rzg2l_pinctrl_register()
1426 pctrl->desc.confops = &rzg2l_pinctrl_confops; in rzg2l_pinctrl_register()
1427 pctrl->desc.owner = THIS_MODULE; in rzg2l_pinctrl_register()
1429 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); in rzg2l_pinctrl_register()
1433 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, in rzg2l_pinctrl_register()
1438 pctrl->pins = pins; in rzg2l_pinctrl_register()
1439 pctrl->desc.pins = pins; in rzg2l_pinctrl_register()
1441 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { in rzg2l_pinctrl_register()
1443 pins[i].name = pctrl->data->port_pins[i]; in rzg2l_pinctrl_register()
1446 pin_data[i] = pctrl->data->port_pin_configs[j]; in rzg2l_pinctrl_register()
1450 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { in rzg2l_pinctrl_register()
1451 unsigned int index = pctrl->data->n_port_pins + i; in rzg2l_pinctrl_register()
1454 pins[index].name = pctrl->data->dedicated_pins[i].name; in rzg2l_pinctrl_register()
1455 pin_data[index] = pctrl->data->dedicated_pins[i].config; in rzg2l_pinctrl_register()
1459 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, in rzg2l_pinctrl_register()
1460 &pctrl->pctl); in rzg2l_pinctrl_register()
1462 dev_err(pctrl->dev, "pinctrl registration failed\n"); in rzg2l_pinctrl_register()
1466 ret = pinctrl_enable(pctrl->pctl); in rzg2l_pinctrl_register()
1468 dev_err(pctrl->dev, "pinctrl enable failed\n"); in rzg2l_pinctrl_register()
1472 ret = rzg2l_gpio_register(pctrl); in rzg2l_pinctrl_register()
1474 dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret); in rzg2l_pinctrl_register()
1483 struct rzg2l_pinctrl *pctrl; in rzg2l_pinctrl_probe() local
1493 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in rzg2l_pinctrl_probe()
1494 if (!pctrl) in rzg2l_pinctrl_probe()
1497 pctrl->dev = &pdev->dev; in rzg2l_pinctrl_probe()
1499 pctrl->data = of_device_get_match_data(&pdev->dev); in rzg2l_pinctrl_probe()
1500 if (!pctrl->data) in rzg2l_pinctrl_probe()
1503 pctrl->base = devm_platform_ioremap_resource(pdev, 0); in rzg2l_pinctrl_probe()
1504 if (IS_ERR(pctrl->base)) in rzg2l_pinctrl_probe()
1505 return PTR_ERR(pctrl->base); in rzg2l_pinctrl_probe()
1507 clk = devm_clk_get_enabled(pctrl->dev, NULL); in rzg2l_pinctrl_probe()
1509 return dev_err_probe(pctrl->dev, PTR_ERR(clk), in rzg2l_pinctrl_probe()
1512 spin_lock_init(&pctrl->lock); in rzg2l_pinctrl_probe()
1513 spin_lock_init(&pctrl->bitmap_lock); in rzg2l_pinctrl_probe()
1514 mutex_init(&pctrl->mutex); in rzg2l_pinctrl_probe()
1516 platform_set_drvdata(pdev, pctrl); in rzg2l_pinctrl_probe()
1518 ret = rzg2l_pinctrl_register(pctrl); in rzg2l_pinctrl_probe()
1522 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); in rzg2l_pinctrl_probe()