Lines Matching refs:pin_reg
42 u32 pin_reg; in amd_gpio_get_direction() local
46 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_get_direction()
49 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) in amd_gpio_get_direction()
58 u32 pin_reg; in amd_gpio_direction_input() local
62 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_direction_input()
63 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); in amd_gpio_direction_input()
64 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_direction_input()
73 u32 pin_reg; in amd_gpio_direction_output() local
78 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_direction_output()
79 pin_reg |= BIT(OUTPUT_ENABLE_OFF); in amd_gpio_direction_output()
81 pin_reg |= BIT(OUTPUT_VALUE_OFF); in amd_gpio_direction_output()
83 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); in amd_gpio_direction_output()
84 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_direction_output()
92 u32 pin_reg; in amd_gpio_get_value() local
97 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_get_value()
100 return !!(pin_reg & BIT(PIN_STS_OFF)); in amd_gpio_get_value()
105 u32 pin_reg; in amd_gpio_set_value() local
110 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_set_value()
112 pin_reg |= BIT(OUTPUT_VALUE_OFF); in amd_gpio_set_value()
114 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); in amd_gpio_set_value()
115 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_set_value()
123 u32 pin_reg; in amd_gpio_set_debounce() local
128 pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); in amd_gpio_set_debounce()
129 if (pin_reg & INTERNAL_GPIO0_DEBOUNCE) in amd_gpio_set_debounce()
133 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_set_debounce()
136 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; in amd_gpio_set_debounce()
137 pin_reg &= ~DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
149 pin_reg |= 1; in amd_gpio_set_debounce()
150 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
151 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
154 pin_reg |= time & DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
155 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
156 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
159 pin_reg |= time & DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
160 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
161 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
164 pin_reg |= time & DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
165 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
166 pin_reg |= BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
169 pin_reg |= time & DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
170 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
171 pin_reg |= BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
173 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); in amd_gpio_set_debounce()
177 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
178 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
179 pin_reg &= ~DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
180 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); in amd_gpio_set_debounce()
182 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_set_debounce()
190 u32 pin_reg; in amd_gpio_dbg_show() local
244 pin_reg = readl(gpio_dev->base + i * 4); in amd_gpio_dbg_show()
247 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { in amd_gpio_dbg_show()
248 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & in amd_gpio_dbg_show()
255 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && in amd_gpio_dbg_show()
261 if (pin_reg & BIT(LEVEL_TRIG_OFF)) in amd_gpio_dbg_show()
266 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) in amd_gpio_dbg_show()
271 if (pin_reg & BIT(INTERRUPT_STS_OFF)) in amd_gpio_dbg_show()
284 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) in amd_gpio_dbg_show()
290 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) in amd_gpio_dbg_show()
296 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) in amd_gpio_dbg_show()
302 if (pin_reg & BIT(WAKECNTRL_Z_OFF)) in amd_gpio_dbg_show()
308 if (pin_reg & BIT(WAKE_STS_OFF)) in amd_gpio_dbg_show()
314 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { in amd_gpio_dbg_show()
316 } else if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) { in amd_gpio_dbg_show()
322 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { in amd_gpio_dbg_show()
324 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) in amd_gpio_dbg_show()
330 if (pin_reg & BIT(PIN_STS_OFF)) in amd_gpio_dbg_show()
337 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg; in amd_gpio_dbg_show()
339 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_dbg_show()
340 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF); in amd_gpio_dbg_show()
341 time = pin_reg & DB_TMR_OUT_MASK; in amd_gpio_dbg_show()
364 seq_printf(s, "0x%x\n", pin_reg); in amd_gpio_dbg_show()
374 u32 pin_reg; in amd_gpio_irq_enable() local
382 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_enable()
383 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); in amd_gpio_irq_enable()
384 pin_reg |= BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_enable()
385 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_enable()
391 u32 pin_reg; in amd_gpio_irq_disable() local
397 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_disable()
398 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); in amd_gpio_irq_disable()
399 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_disable()
400 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_disable()
408 u32 pin_reg; in amd_gpio_irq_mask() local
414 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_mask()
415 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_mask()
416 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_mask()
422 u32 pin_reg; in amd_gpio_irq_unmask() local
428 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_unmask()
429 pin_reg |= BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_unmask()
430 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_unmask()
436 u32 pin_reg; in amd_gpio_irq_set_wake() local
444 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_set_wake()
447 pin_reg |= wake_mask; in amd_gpio_irq_set_wake()
449 pin_reg &= ~wake_mask; in amd_gpio_irq_set_wake()
451 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_set_wake()
483 u32 pin_reg, pin_reg_irq_en, mask; in amd_gpio_irq_set_type() local
489 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_set_type()
493 pin_reg &= ~BIT(LEVEL_TRIG_OFF); in amd_gpio_irq_set_type()
494 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
495 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
500 pin_reg &= ~BIT(LEVEL_TRIG_OFF); in amd_gpio_irq_set_type()
501 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
502 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
507 pin_reg &= ~BIT(LEVEL_TRIG_OFF); in amd_gpio_irq_set_type()
508 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
509 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
514 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; in amd_gpio_irq_set_type()
515 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
516 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
521 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; in amd_gpio_irq_set_type()
522 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
523 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
535 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; in amd_gpio_irq_set_type()
552 pin_reg_irq_en = pin_reg; in amd_gpio_irq_set_type()
558 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_set_type()
724 u32 pin_reg; in amd_pinconf_get() local
731 pin_reg = readl(gpio_dev->base + pin*4); in amd_pinconf_get()
735 arg = pin_reg & DB_TMR_OUT_MASK; in amd_pinconf_get()
739 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); in amd_pinconf_get()
743 arg = (pin_reg >> PULL_UP_ENABLE_OFF) & BIT(0); in amd_pinconf_get()
747 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; in amd_pinconf_get()
767 u32 pin_reg; in amd_pinconf_set() local
776 pin_reg = readl(gpio_dev->base + pin*4); in amd_pinconf_set()
784 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); in amd_pinconf_set()
785 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; in amd_pinconf_set()
789 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); in amd_pinconf_set()
790 pin_reg |= (arg & BIT(0)) << PULL_UP_ENABLE_OFF; in amd_pinconf_set()
794 pin_reg &= ~(DRV_STRENGTH_SEL_MASK in amd_pinconf_set()
796 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) in amd_pinconf_set()
806 writel(pin_reg, gpio_dev->base + pin*4); in amd_pinconf_set()
869 u32 pin_reg, mask; in amd_gpio_irq_init() local
884 pin_reg = readl(gpio_dev->base + pin * 4); in amd_gpio_irq_init()
885 pin_reg &= ~mask; in amd_gpio_irq_init()
886 writel(pin_reg, gpio_dev->base + pin * 4); in amd_gpio_irq_init()