Lines Matching +full:gpio1 +full:- +full:cfg
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2016-2018 Nuvoton Technology corporation.
21 #include <linux/pinctrl/pinconf-generic.h>
51 #define NPCM7XX_GP_N_PU 0x1c /* Pull-up */
52 #define NPCM7XX_GP_N_PD 0x20 /* Pull-down */
110 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in npcm_gpio_set()
115 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in npcm_gpio_set()
124 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in npcm_gpio_clr()
129 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in npcm_gpio_clr()
136 seq_printf(s, "-- module %d [gpio%d - %d]\n", in npcmgpio_dbg_show()
137 bank->gc.base / bank->gc.ngpio, in npcmgpio_dbg_show()
138 bank->gc.base, in npcmgpio_dbg_show()
139 bank->gc.base + bank->gc.ngpio); in npcmgpio_dbg_show()
141 ioread32(bank->base + NPCM7XX_GP_N_DIN), in npcmgpio_dbg_show()
142 ioread32(bank->base + NPCM7XX_GP_N_DOUT), in npcmgpio_dbg_show()
143 ioread32(bank->base + NPCM7XX_GP_N_IEM), in npcmgpio_dbg_show()
144 ioread32(bank->base + NPCM7XX_GP_N_OE)); in npcmgpio_dbg_show()
146 ioread32(bank->base + NPCM7XX_GP_N_PU), in npcmgpio_dbg_show()
147 ioread32(bank->base + NPCM7XX_GP_N_PD), in npcmgpio_dbg_show()
148 ioread32(bank->base + NPCM7XX_GP_N_DBNC), in npcmgpio_dbg_show()
149 ioread32(bank->base + NPCM7XX_GP_N_POL)); in npcmgpio_dbg_show()
151 ioread32(bank->base + NPCM7XX_GP_N_EVTYP), in npcmgpio_dbg_show()
152 ioread32(bank->base + NPCM7XX_GP_N_EVBE), in npcmgpio_dbg_show()
153 ioread32(bank->base + NPCM7XX_GP_N_EVEN), in npcmgpio_dbg_show()
154 ioread32(bank->base + NPCM7XX_GP_N_EVST)); in npcmgpio_dbg_show()
156 ioread32(bank->base + NPCM7XX_GP_N_OTYP), in npcmgpio_dbg_show()
157 ioread32(bank->base + NPCM7XX_GP_N_OSRC), in npcmgpio_dbg_show()
158 ioread32(bank->base + NPCM7XX_GP_N_ODSC)); in npcmgpio_dbg_show()
160 ioread32(bank->base + NPCM7XX_GP_N_OBL0), in npcmgpio_dbg_show()
161 ioread32(bank->base + NPCM7XX_GP_N_OBL1), in npcmgpio_dbg_show()
162 ioread32(bank->base + NPCM7XX_GP_N_OBL2), in npcmgpio_dbg_show()
163 ioread32(bank->base + NPCM7XX_GP_N_OBL3)); in npcmgpio_dbg_show()
165 ioread32(bank->base + NPCM7XX_GP_N_SPLCK), in npcmgpio_dbg_show()
166 ioread32(bank->base + NPCM7XX_GP_N_MPLCK)); in npcmgpio_dbg_show()
174 ret = pinctrl_gpio_direction_input(offset + chip->base); in npcmgpio_direction_input()
178 return bank->direction_input(chip, offset); in npcmgpio_direction_input()
188 dev_dbg(chip->parent, "gpio_direction_output: offset%d = %x\n", offset, in npcmgpio_direction_output()
191 ret = pinctrl_gpio_direction_output(offset + chip->base); in npcmgpio_direction_output()
195 return bank->direction_output(chip, offset, value); in npcmgpio_direction_output()
203 dev_dbg(chip->parent, "gpio_request: offset%d\n", offset); in npcmgpio_gpio_request()
204 ret = pinctrl_gpio_request(offset + chip->base); in npcmgpio_gpio_request()
208 return bank->request(chip, offset); in npcmgpio_gpio_request()
213 dev_dbg(chip->parent, "gpio_free: offset%d\n", offset); in npcmgpio_gpio_free()
214 pinctrl_gpio_free(offset + chip->base); in npcmgpio_gpio_free()
229 sts = ioread32(bank->base + NPCM7XX_GP_N_EVST); in npcmgpio_irq_handler()
230 en = ioread32(bank->base + NPCM7XX_GP_N_EVEN); in npcmgpio_irq_handler()
231 dev_dbg(bank->gc.parent, "==> got irq sts %.8lx %.8lx\n", sts, in npcmgpio_irq_handler()
236 generic_handle_domain_irq(gc->irq.domain, bit); in npcmgpio_irq_handler()
246 dev_dbg(bank->gc.parent, "setirqtype: %u.%u = %u\n", gpio, in npcmgpio_set_irq_type()
247 d->irq, type); in npcmgpio_set_irq_type()
250 dev_dbg(bank->gc.parent, "edge.rising\n"); in npcmgpio_set_irq_type()
251 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); in npcmgpio_set_irq_type()
252 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); in npcmgpio_set_irq_type()
255 dev_dbg(bank->gc.parent, "edge.falling\n"); in npcmgpio_set_irq_type()
256 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); in npcmgpio_set_irq_type()
257 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); in npcmgpio_set_irq_type()
260 dev_dbg(bank->gc.parent, "edge.both\n"); in npcmgpio_set_irq_type()
261 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); in npcmgpio_set_irq_type()
264 dev_dbg(bank->gc.parent, "level.low\n"); in npcmgpio_set_irq_type()
265 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); in npcmgpio_set_irq_type()
268 dev_dbg(bank->gc.parent, "level.high\n"); in npcmgpio_set_irq_type()
269 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); in npcmgpio_set_irq_type()
272 dev_dbg(bank->gc.parent, "invalid irq type\n"); in npcmgpio_set_irq_type()
273 return -EINVAL; in npcmgpio_set_irq_type()
277 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio); in npcmgpio_set_irq_type()
281 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio); in npcmgpio_set_irq_type()
294 dev_dbg(bank->gc.parent, "irq_ack: %u.%u\n", gpio, d->irq); in npcmgpio_irq_ack()
295 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVST); in npcmgpio_irq_ack()
306 dev_dbg(bank->gc.parent, "irq_mask: %u.%u\n", gpio, d->irq); in npcmgpio_irq_mask()
307 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENC); in npcmgpio_irq_mask()
320 dev_dbg(bank->gc.parent, "irq_unmask: %u.%u\n", gpio, d->irq); in npcmgpio_irq_unmask()
321 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENS); in npcmgpio_irq_unmask()
329 /* active-high, input, clear interrupt, enable interrupt */ in npcmgpio_irq_startup()
330 dev_dbg(gc->parent, "startup: %u.%u\n", gpio, d->irq); in npcmgpio_irq_startup()
339 .name = "NPCM7XX-GPIO-IRQ",
1178 PINCTRL_PIN(1, "GPIO1/IOX1LD"),
1421 const struct npcm7xx_pincfg *cfg; in npcm7xx_setfunc() local
1425 cfg = &pincfg[pin[i]]; in npcm7xx_setfunc()
1426 if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode || cfg->fn2 == mode) { in npcm7xx_setfunc()
1427 if (cfg->reg0) in npcm7xx_setfunc()
1428 regmap_update_bits(gcr_regmap, cfg->reg0, in npcm7xx_setfunc()
1429 BIT(cfg->bit0), in npcm7xx_setfunc()
1430 !!(cfg->fn0 == mode) ? in npcm7xx_setfunc()
1431 BIT(cfg->bit0) : 0); in npcm7xx_setfunc()
1432 if (cfg->reg1) in npcm7xx_setfunc()
1433 regmap_update_bits(gcr_regmap, cfg->reg1, in npcm7xx_setfunc()
1434 BIT(cfg->bit1), in npcm7xx_setfunc()
1435 !!(cfg->fn1 == mode) ? in npcm7xx_setfunc()
1436 BIT(cfg->bit1) : 0); in npcm7xx_setfunc()
1437 if (cfg->reg2) in npcm7xx_setfunc()
1438 regmap_update_bits(gcr_regmap, cfg->reg2, in npcm7xx_setfunc()
1439 BIT(cfg->bit2), in npcm7xx_setfunc()
1440 !!(cfg->fn2 == mode) ? in npcm7xx_setfunc()
1441 BIT(cfg->bit2) : 0); in npcm7xx_setfunc()
1451 int gpio = (pin % bank->gc.ngpio); in npcm7xx_get_slew_rate()
1455 return ioread32(bank->base + NPCM7XX_GP_N_OSRC) in npcm7xx_get_slew_rate()
1463 return -EINVAL; in npcm7xx_get_slew_rate()
1471 int gpio = BIT(pin % bank->gc.ngpio); in npcm7xx_set_slew_rate()
1476 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC, in npcm7xx_set_slew_rate()
1480 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC, in npcm7xx_set_slew_rate()
1484 return -EINVAL; in npcm7xx_set_slew_rate()
1499 return -EINVAL; in npcm7xx_set_slew_rate()
1503 return -EINVAL; in npcm7xx_set_slew_rate()
1512 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; in npcm7xx_get_drive_strength()
1513 int gpio = (pin % bank->gc.ngpio); in npcm7xx_get_drive_strength()
1521 val = ioread32(bank->base + NPCM7XX_GP_N_ODSC) in npcm7xx_get_drive_strength()
1524 dev_dbg(bank->gc.parent, in npcm7xx_get_drive_strength()
1529 return -EINVAL; in npcm7xx_get_drive_strength()
1538 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; in npcm7xx_set_drive_strength()
1539 int gpio = BIT(pin % bank->gc.ngpio); in npcm7xx_set_drive_strength()
1543 return -ENOTSUPP; in npcm7xx_set_drive_strength()
1545 dev_dbg(bank->gc.parent, in npcm7xx_set_drive_strength()
1547 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio); in npcm7xx_set_drive_strength()
1550 dev_dbg(bank->gc.parent, in npcm7xx_set_drive_strength()
1552 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio); in npcm7xx_set_drive_strength()
1556 return -ENOTSUPP; in npcm7xx_set_drive_strength()
1570 dev_dbg(npcm->dev, "group size: %zu\n", ARRAY_SIZE(npcm7xx_groups)); in npcm7xx_get_groups_count()
1598 dev_dbg(npcm->dev, "dt_node_to_map: %s\n", np_config->name); in npcm7xx_dt_node_to_map()
1648 dev_dbg(npcm->dev, "set_mux: %d, %d[%s]\n", function, group, in npcm7xx_pinmux_set_mux()
1651 npcm7xx_setfunc(npcm->gcr_regmap, npcm7xx_groups[group].pins, in npcm7xx_pinmux_set_mux()
1664 dev_err(npcm->dev, "invalid range\n"); in npcm7xx_gpio_request_enable()
1665 return -EINVAL; in npcm7xx_gpio_request_enable()
1667 if (!range->gc) { in npcm7xx_gpio_request_enable()
1668 dev_err(npcm->dev, "invalid gpiochip\n"); in npcm7xx_gpio_request_enable()
1669 return -EINVAL; in npcm7xx_gpio_request_enable()
1672 npcm7xx_setfunc(npcm->gcr_regmap, &offset, 1, fn_gpio); in npcm7xx_gpio_request_enable()
1685 virq = irq_find_mapping(npcm->domain, offset); in npcm7xx_gpio_request_free()
1697 &npcm->gpio_bank[offset / NPCM7XX_GPIO_PER_BANK]; in npcm_gpio_set_direction()
1698 int gpio = BIT(offset % bank->gc.ngpio); in npcm_gpio_set_direction()
1700 dev_dbg(bank->gc.parent, "GPIO Set Direction: %d = %d\n", offset, in npcm_gpio_set_direction()
1703 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC); in npcm_gpio_set_direction()
1705 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES); in npcm_gpio_set_direction()
1727 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; in npcm7xx_config_get()
1728 int gpio = (pin % bank->gc.ngpio); in npcm7xx_config_get()
1737 pu = ioread32(bank->base + NPCM7XX_GP_N_PU) & pinmask; in npcm7xx_config_get()
1738 pd = ioread32(bank->base + NPCM7XX_GP_N_PD) & pinmask; in npcm7xx_config_get()
1748 ie = ioread32(bank->base + NPCM7XX_GP_N_IEM) & pinmask; in npcm7xx_config_get()
1749 oe = ioread32(bank->base + NPCM7XX_GP_N_OE) & pinmask; in npcm7xx_config_get()
1756 rc = !(ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask); in npcm7xx_config_get()
1759 rc = ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask; in npcm7xx_config_get()
1762 rc = ioread32(bank->base + NPCM7XX_GP_N_DBNC) & pinmask; in npcm7xx_config_get()
1770 rc = npcm7xx_get_slew_rate(bank, npcm->gcr_regmap, pin); in npcm7xx_config_get()
1775 return -ENOTSUPP; in npcm7xx_config_get()
1779 return -EINVAL; in npcm7xx_config_get()
1790 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; in npcm7xx_config_set_one()
1791 int gpio = BIT(pin % bank->gc.ngpio); in npcm7xx_config_set_one()
1793 dev_dbg(bank->gc.parent, "param=%d %d[GPIO]\n", param, pin); in npcm7xx_config_set_one()
1796 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); in npcm7xx_config_set_one()
1797 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); in npcm7xx_config_set_one()
1800 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); in npcm7xx_config_set_one()
1801 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); in npcm7xx_config_set_one()
1804 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); in npcm7xx_config_set_one()
1805 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); in npcm7xx_config_set_one()
1808 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC); in npcm7xx_config_set_one()
1809 bank->direction_input(&bank->gc, pin % bank->gc.ngpio); in npcm7xx_config_set_one()
1812 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES); in npcm7xx_config_set_one()
1813 bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg); in npcm7xx_config_set_one()
1816 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio); in npcm7xx_config_set_one()
1819 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio); in npcm7xx_config_set_one()
1822 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_DBNC, gpio); in npcm7xx_config_set_one()
1825 return npcm7xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg); in npcm7xx_config_set_one()
1829 return -ENOTSUPP; in npcm7xx_config_set_one()
1842 while (num_configs--) { in npcm7xx_config_set()
1859 .name = "npcm7xx-pinctrl",
1870 int ret = -ENXIO; in npcm7xx_gpio_of()
1872 struct device *dev = pctrl->dev; in npcm7xx_gpio_of()
1886 pctrl->gpio_bank[id].base = ioremap(res.start, resource_size(&res)); in npcm7xx_gpio_of()
1887 if (!pctrl->gpio_bank[id].base) in npcm7xx_gpio_of()
1888 return -EINVAL; in npcm7xx_gpio_of()
1890 ret = bgpio_init(&pctrl->gpio_bank[id].gc, dev, 4, in npcm7xx_gpio_of()
1891 pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DIN, in npcm7xx_gpio_of()
1892 pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DOUT, in npcm7xx_gpio_of()
1895 pctrl->gpio_bank[id].base + NPCM7XX_GP_N_IEM, in npcm7xx_gpio_of()
1902 ret = fwnode_property_get_reference_args(child, "gpio-ranges", NULL, 3, 0, &args); in npcm7xx_gpio_of()
1904 dev_err(dev, "gpio-ranges fail for GPIO bank %u\n", id); in npcm7xx_gpio_of()
1911 return -EINVAL; in npcm7xx_gpio_of()
1913 pctrl->gpio_bank[id].irq = ret; in npcm7xx_gpio_of()
1914 pctrl->gpio_bank[id].irqbase = id * NPCM7XX_GPIO_PER_BANK; in npcm7xx_gpio_of()
1915 pctrl->gpio_bank[id].pinctrl_id = args.args[0]; in npcm7xx_gpio_of()
1916 pctrl->gpio_bank[id].gc.base = args.args[1]; in npcm7xx_gpio_of()
1917 pctrl->gpio_bank[id].gc.ngpio = args.args[2]; in npcm7xx_gpio_of()
1918 pctrl->gpio_bank[id].gc.owner = THIS_MODULE; in npcm7xx_gpio_of()
1919 pctrl->gpio_bank[id].gc.parent = dev; in npcm7xx_gpio_of()
1920 pctrl->gpio_bank[id].gc.fwnode = child; in npcm7xx_gpio_of()
1921 pctrl->gpio_bank[id].gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child); in npcm7xx_gpio_of()
1922 if (pctrl->gpio_bank[id].gc.label == NULL) in npcm7xx_gpio_of()
1923 return -ENOMEM; in npcm7xx_gpio_of()
1925 pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show; in npcm7xx_gpio_of()
1926 pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].gc.direction_input; in npcm7xx_gpio_of()
1927 pctrl->gpio_bank[id].gc.direction_input = npcmgpio_direction_input; in npcm7xx_gpio_of()
1928 pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].gc.direction_output; in npcm7xx_gpio_of()
1929 pctrl->gpio_bank[id].gc.direction_output = npcmgpio_direction_output; in npcm7xx_gpio_of()
1930 pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].gc.request; in npcm7xx_gpio_of()
1931 pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request; in npcm7xx_gpio_of()
1932 pctrl->gpio_bank[id].gc.free = npcmgpio_gpio_free; in npcm7xx_gpio_of()
1936 pctrl->bank_num = id; in npcm7xx_gpio_of()
1944 for (id = 0 ; id < pctrl->bank_num ; id++) { in npcm7xx_gpio_register()
1947 girq = &pctrl->gpio_bank[id].gc.irq; in npcm7xx_gpio_register()
1949 girq->parent_handler = npcmgpio_irq_handler; in npcm7xx_gpio_register()
1950 girq->num_parents = 1; in npcm7xx_gpio_register()
1951 girq->parents = devm_kcalloc(pctrl->dev, 1, in npcm7xx_gpio_register()
1952 sizeof(*girq->parents), in npcm7xx_gpio_register()
1954 if (!girq->parents) { in npcm7xx_gpio_register()
1955 ret = -ENOMEM; in npcm7xx_gpio_register()
1958 girq->parents[0] = pctrl->gpio_bank[id].irq; in npcm7xx_gpio_register()
1959 girq->default_type = IRQ_TYPE_NONE; in npcm7xx_gpio_register()
1960 girq->handler = handle_level_irq; in npcm7xx_gpio_register()
1961 ret = devm_gpiochip_add_data(pctrl->dev, in npcm7xx_gpio_register()
1962 &pctrl->gpio_bank[id].gc, in npcm7xx_gpio_register()
1963 &pctrl->gpio_bank[id]); in npcm7xx_gpio_register()
1965 dev_err(pctrl->dev, "Failed to add GPIO chip %u\n", id); in npcm7xx_gpio_register()
1969 ret = gpiochip_add_pin_range(&pctrl->gpio_bank[id].gc, in npcm7xx_gpio_register()
1970 dev_name(pctrl->dev), in npcm7xx_gpio_register()
1971 pctrl->gpio_bank[id].pinctrl_id, in npcm7xx_gpio_register()
1972 pctrl->gpio_bank[id].gc.base, in npcm7xx_gpio_register()
1973 pctrl->gpio_bank[id].gc.ngpio); in npcm7xx_gpio_register()
1975 dev_err(pctrl->dev, "Failed to add GPIO bank %u\n", id); in npcm7xx_gpio_register()
1976 gpiochip_remove(&pctrl->gpio_bank[id].gc); in npcm7xx_gpio_register()
1984 for (; id > 0; id--) in npcm7xx_gpio_register()
1985 gpiochip_remove(&pctrl->gpio_bank[id - 1].gc); in npcm7xx_gpio_register()
1995 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in npcm7xx_pinctrl_probe()
1997 return -ENOMEM; in npcm7xx_pinctrl_probe()
1999 pctrl->dev = &pdev->dev; in npcm7xx_pinctrl_probe()
2000 dev_set_drvdata(&pdev->dev, pctrl); in npcm7xx_pinctrl_probe()
2002 pctrl->gcr_regmap = in npcm7xx_pinctrl_probe()
2003 syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr"); in npcm7xx_pinctrl_probe()
2004 if (IS_ERR(pctrl->gcr_regmap)) { in npcm7xx_pinctrl_probe()
2005 dev_err(pctrl->dev, "didn't find nuvoton,npcm750-gcr\n"); in npcm7xx_pinctrl_probe()
2006 return PTR_ERR(pctrl->gcr_regmap); in npcm7xx_pinctrl_probe()
2011 dev_err(pctrl->dev, "Failed to gpio dt-binding %u\n", ret); in npcm7xx_pinctrl_probe()
2015 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, in npcm7xx_pinctrl_probe()
2017 if (IS_ERR(pctrl->pctldev)) { in npcm7xx_pinctrl_probe()
2018 dev_err(&pdev->dev, "Failed to register pinctrl device\n"); in npcm7xx_pinctrl_probe()
2019 return PTR_ERR(pctrl->pctldev); in npcm7xx_pinctrl_probe()
2024 dev_err(pctrl->dev, "Failed to register gpio %u\n", ret); in npcm7xx_pinctrl_probe()
2033 { .compatible = "nuvoton,npcm750-pinctrl" },
2041 .name = "npcm7xx-pinctrl",