Lines Matching refs:DRV_BASE1

17 #define DRV_BASE1				0x500  macro
59 	MTK_PIN_DRV_GRP(0, DRV_BASE1, 0, 0),
60 	MTK_PIN_DRV_GRP(1, DRV_BASE1, 0, 0),
61 	MTK_PIN_DRV_GRP(2, DRV_BASE1, 0, 0),
62 	MTK_PIN_DRV_GRP(3, DRV_BASE1, 0, 0),
63 	MTK_PIN_DRV_GRP(4, DRV_BASE1, 4, 0),
64 	MTK_PIN_DRV_GRP(5, DRV_BASE1, 8, 0),
65 	MTK_PIN_DRV_GRP(6, DRV_BASE1, 0, 0),
66 	MTK_PIN_DRV_GRP(7, DRV_BASE1, 0, 0),
67 	MTK_PIN_DRV_GRP(8, DRV_BASE1, 0, 0),
68 	MTK_PIN_DRV_GRP(9, DRV_BASE1, 0, 0),
70 	MTK_PIN_DRV_GRP(10, DRV_BASE1, 12, 1),
71 	MTK_PIN_DRV_GRP(11, DRV_BASE1, 12, 1),
72 	MTK_PIN_DRV_GRP(12, DRV_BASE1, 12, 1),
73 	MTK_PIN_DRV_GRP(13, DRV_BASE1, 12, 1),
74 	MTK_PIN_DRV_GRP(14, DRV_BASE1, 12, 1),
75 	MTK_PIN_DRV_GRP(15, DRV_BASE1, 12, 1),
76 	MTK_PIN_DRV_GRP(16, DRV_BASE1, 12, 1),
77 	MTK_PIN_DRV_GRP(17, DRV_BASE1, 16, 1),
78 	MTK_PIN_DRV_GRP(18, DRV_BASE1, 16, 1),
79 	MTK_PIN_DRV_GRP(19, DRV_BASE1, 16, 1),
80 	MTK_PIN_DRV_GRP(20, DRV_BASE1, 16, 1),
81 	MTK_PIN_DRV_GRP(21, DRV_BASE1, 16, 1),
82 	MTK_PIN_DRV_GRP(22, DRV_BASE1, 16, 1),
83 	MTK_PIN_DRV_GRP(23, DRV_BASE1, 16, 1),
84 	MTK_PIN_DRV_GRP(24, DRV_BASE1, 16, 1),
85 	MTK_PIN_DRV_GRP(33, DRV_BASE1, 24, 1),
153 	MTK_PIN_DRV_GRP(96, DRV_BASE1+0xb0, 28, 0),
181 	MTK_PIN_DRV_GRP(181, DRV_BASE1+0xa0, 12, 1),
182 	MTK_PIN_DRV_GRP(182, DRV_BASE1+0xa0, 16, 1),
183 	MTK_PIN_DRV_GRP(183, DRV_BASE1+0xa0, 20, 1),
184 	MTK_PIN_DRV_GRP(184, DRV_BASE1+0xa0, 24, 1),
185 	MTK_PIN_DRV_GRP(185, DRV_BASE1+0xa0, 28, 1),
187 	MTK_PIN_DRV_GRP(186, DRV_BASE1+0xb0, 0, 2),
188 	MTK_PIN_DRV_GRP(187, DRV_BASE1+0xb0, 0, 2),
189 	MTK_PIN_DRV_GRP(188, DRV_BASE1+0xb0, 0, 2),
190 	MTK_PIN_DRV_GRP(189, DRV_BASE1+0xb0, 0, 2),
191 	MTK_PIN_DRV_GRP(190, DRV_BASE1+0xb0, 4, 1),
192 	MTK_PIN_DRV_GRP(191, DRV_BASE1+0xb0, 8, 1),
193 	MTK_PIN_DRV_GRP(192, DRV_BASE1+0xb0, 12, 1),
195 	MTK_PIN_DRV_GRP(197, DRV_BASE1+0xb0, 16, 0),
196 	MTK_PIN_DRV_GRP(198, DRV_BASE1+0xb0, 16, 0),
197 	MTK_PIN_DRV_GRP(199, DRV_BASE1+0xb0, 20, 0),
198 	MTK_PIN_DRV_GRP(200, DRV_BASE1+0xb0, 24, 0),
199 	MTK_PIN_DRV_GRP(201, DRV_BASE1+0xb0, 16, 0),
200 	MTK_PIN_DRV_GRP(202, DRV_BASE1+0xb0, 16, 0)