Lines Matching +full:trig +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013, Intel Corporation
27 #include <linux/pinctrl/pinconf-generic.h>
29 #include "pinctrl-intel.h"
564 offset -= comm->pin_base; in byt_gpio_reg()
573 reg_offset = comm->pad_map[offset] * 16; in byt_gpio_reg()
577 return comm->pad_regs + reg_offset + reg; in byt_gpio_reg()
601 dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n", in byt_set_group_simple_mux()
630 dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n", in byt_set_group_mixed_mux()
648 const struct intel_function func = vg->soc->functions[func_selector]; in byt_set_mux()
649 const struct intel_pingroup group = vg->soc->groups[group_selector]; in byt_set_mux()
663 /* SCORE pin 92-93 */ in byt_get_gpio_mux()
664 if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) && in byt_get_gpio_mux()
668 /* SUS pin 11-21 */ in byt_get_gpio_mux()
669 if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) && in byt_get_gpio_mux()
685 /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */ in byt_gpio_clear_triggering()
720 dev_warn(vg->dev, FW_BUG "Pin %i: forcibly re-configured as GPIO\n", offset); in byt_gpio_request_enable()
725 pm_runtime_get(vg->dev); in byt_gpio_request_enable()
737 pm_runtime_put(vg->dev); in byt_gpio_disable_free()
752 dev_info_once(vg->dev, in byt_gpio_direct_irq_check()
829 return -EINVAL; in byt_set_pull_strength()
856 return -EINVAL; in byt_pin_config_get()
861 return -EINVAL; in byt_pin_config_get()
869 return -EINVAL; in byt_pin_config_get()
876 return -EINVAL; in byt_pin_config_get()
905 return -EINVAL; in byt_pin_config_get()
910 return -ENOTSUPP; in byt_pin_config_get()
957 dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset); in byt_pin_config_set()
977 dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset); in byt_pin_config_set()
1015 ret = -EINVAL; in byt_pin_config_set()
1028 ret = -ENOTSUPP; in byt_pin_config_set()
1097 return -EINVAL; in byt_gpio_get_direction()
1108 return -EINVAL; in byt_gpio_get_direction()
1166 for (i = 0; i < vg->soc->npins; i++) { in byt_gpio_dbg_show()
1175 pin = vg->soc->pins[i].number; in byt_gpio_dbg_show()
1228 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s", in byt_gpio_dbg_show()
1234 comm->pad_map[i], comm->pad_map[i] * 16, in byt_gpio_dbg_show()
1241 seq_printf(s, " %-4s %-3s", pull, pull_str); in byt_gpio_dbg_show()
1246 seq_puts(s, " open-drain"); in byt_gpio_dbg_show()
1342 return -EINVAL; in byt_irq_type()
1372 .name = "BYT-GPIO",
1391 for (base = 0; base < vg->chip.ngpio; base += 32) { in byt_gpio_irq_handler()
1395 dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base); in byt_gpio_irq_handler()
1403 generic_handle_domain_irq(vg->chip.irq.domain, base + pin); in byt_gpio_irq_handler()
1405 chip->irq_eoi(data); in byt_gpio_irq_handler()
1412 u32 trig; in byt_direct_irq_sanity_check() local
1414 memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG, in byt_direct_irq_sanity_check()
1418 dev_warn(vg->dev, FW_BUG "Pin %i: DIRECT_IRQ_EN set but no IRQ assigned, clearing\n", pin); in byt_direct_irq_sanity_check()
1422 direct_irq = match - direct_irq_mux; in byt_direct_irq_sanity_check()
1423 /* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */ in byt_direct_irq_sanity_check()
1424 ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67; in byt_direct_irq_sanity_check()
1425 dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n", pin, in byt_direct_irq_sanity_check()
1430 * direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ in byt_direct_irq_sanity_check()
1432 * 0x800, to one of the IO-APIC pins according to the mux registers. in byt_direct_irq_sanity_check()
1437 * passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set, in byt_direct_irq_sanity_check()
1438 * selecting edge mode operation then on the first edge the IO-APIC pin goes in byt_direct_irq_sanity_check()
1439 * high, but since no write-to-clear write will be done to the IRQ status reg in byt_direct_irq_sanity_check()
1442 trig = conf0 & BYT_TRIG_MASK; in byt_direct_irq_sanity_check()
1443 if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) && in byt_direct_irq_sanity_check()
1444 trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) { in byt_direct_irq_sanity_check()
1445 dev_warn(vg->dev, in byt_direct_irq_sanity_check()
1464 * Clear interrupt triggers for all pins that are GPIOs and in byt_init_irq_valid_mask()
1468 for (i = 0; i < vg->soc->npins; i++) { in byt_init_irq_valid_mask()
1469 unsigned int pin = vg->soc->pins[i].number; in byt_init_irq_valid_mask()
1473 dev_warn(vg->dev, "Pin %i: could not retrieve CONF0\n", i); in byt_init_irq_valid_mask()
1488 dev_dbg(vg->dev, "disabling GPIO %d\n", i); in byt_init_irq_valid_mask()
1500 for (base = 0; base < vg->soc->npins; base += 32) { in byt_gpio_irq_init_hw()
1504 dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base); in byt_gpio_irq_init_hw()
1513 dev_err(vg->dev, in byt_gpio_irq_init_hw()
1524 struct device *dev = vg->dev; in byt_gpio_add_pin_ranges()
1527 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins); in byt_gpio_add_pin_ranges()
1536 struct platform_device *pdev = to_platform_device(vg->dev); in byt_gpio_probe()
1541 vg->chip = byt_gpio_chip; in byt_gpio_probe()
1542 gc = &vg->chip; in byt_gpio_probe()
1543 gc->label = dev_name(vg->dev); in byt_gpio_probe()
1544 gc->base = -1; in byt_gpio_probe()
1545 gc->can_sleep = false; in byt_gpio_probe()
1546 gc->add_pin_ranges = byt_gpio_add_pin_ranges; in byt_gpio_probe()
1547 gc->parent = vg->dev; in byt_gpio_probe()
1548 gc->ngpio = vg->soc->npins; in byt_gpio_probe()
1551 vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads), in byt_gpio_probe()
1553 if (!vg->context.pads) in byt_gpio_probe()
1554 return -ENOMEM; in byt_gpio_probe()
1562 girq = &gc->irq; in byt_gpio_probe()
1564 girq->init_hw = byt_gpio_irq_init_hw; in byt_gpio_probe()
1565 girq->init_valid_mask = byt_init_irq_valid_mask; in byt_gpio_probe()
1566 girq->parent_handler = byt_gpio_irq_handler; in byt_gpio_probe()
1567 girq->num_parents = 1; in byt_gpio_probe()
1568 girq->parents = devm_kcalloc(vg->dev, girq->num_parents, in byt_gpio_probe()
1569 sizeof(*girq->parents), GFP_KERNEL); in byt_gpio_probe()
1570 if (!girq->parents) in byt_gpio_probe()
1571 return -ENOMEM; in byt_gpio_probe()
1572 girq->parents[0] = irq; in byt_gpio_probe()
1573 girq->default_type = IRQ_TYPE_NONE; in byt_gpio_probe()
1574 girq->handler = handle_bad_irq; in byt_gpio_probe()
1577 ret = devm_gpiochip_add_data(vg->dev, gc, vg); in byt_gpio_probe()
1579 dev_err(vg->dev, "failed adding byt-gpio chip\n"); in byt_gpio_probe()
1589 struct platform_device *pdev = to_platform_device(vg->dev); in byt_set_soc_data()
1592 vg->soc = soc; in byt_set_soc_data()
1594 vg->ncommunities = vg->soc->ncommunities; in byt_set_soc_data()
1595 vg->communities = devm_kcalloc(vg->dev, vg->ncommunities, in byt_set_soc_data()
1596 sizeof(*vg->communities), GFP_KERNEL); in byt_set_soc_data()
1597 if (!vg->communities) in byt_set_soc_data()
1598 return -ENOMEM; in byt_set_soc_data()
1600 for (i = 0; i < vg->soc->ncommunities; i++) { in byt_set_soc_data()
1601 struct intel_community *comm = vg->communities + i; in byt_set_soc_data()
1603 *comm = vg->soc->communities[i]; in byt_set_soc_data()
1605 comm->pad_regs = devm_platform_ioremap_resource(pdev, 0); in byt_set_soc_data()
1606 if (IS_ERR(comm->pad_regs)) in byt_set_soc_data()
1607 return PTR_ERR(comm->pad_regs); in byt_set_soc_data()
1622 struct device *dev = &pdev->dev; in byt_pinctrl_probe()
1632 return -ENOMEM; in byt_pinctrl_probe()
1634 vg->dev = dev; in byt_pinctrl_probe()
1641 vg->pctldesc = byt_pinctrl_desc; in byt_pinctrl_probe()
1642 vg->pctldesc.name = dev_name(dev); in byt_pinctrl_probe()
1643 vg->pctldesc.pins = vg->soc->pins; in byt_pinctrl_probe()
1644 vg->pctldesc.npins = vg->soc->npins; in byt_pinctrl_probe()
1646 vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg); in byt_pinctrl_probe()
1647 if (IS_ERR(vg->pctldev)) { in byt_pinctrl_probe()
1649 return PTR_ERR(vg->pctldev); in byt_pinctrl_probe()
1670 for (i = 0; i < vg->soc->npins; i++) { in byt_gpio_suspend()
1673 unsigned int pin = vg->soc->pins[i].number; in byt_gpio_suspend()
1677 dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i); in byt_gpio_suspend()
1681 vg->context.pads[i].conf0 = value; in byt_gpio_suspend()
1685 dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i); in byt_gpio_suspend()
1689 vg->context.pads[i].val = value; in byt_gpio_suspend()
1704 for (i = 0; i < vg->soc->npins; i++) { in byt_gpio_resume()
1707 unsigned int pin = vg->soc->pins[i].number; in byt_gpio_resume()
1711 dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i); in byt_gpio_resume()
1716 vg->context.pads[i].conf0) { in byt_gpio_resume()
1718 value |= vg->context.pads[i].conf0; in byt_gpio_resume()
1725 dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i); in byt_gpio_resume()
1730 vg->context.pads[i].val) { in byt_gpio_resume()
1734 v |= vg->context.pads[i].val; in byt_gpio_resume()