Lines Matching +full:enable +full:- +full:ssc
1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
32 /* TX De-emphasis parameters */
61 /* PLL SSC step size offsets */
70 /* SSC step size parameters */
171 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
174 * @steps: number of steps of SSC (Spread Spectrum Clock)
185 * struct xpsgtr_phy - representation of a lane
205 * struct xpsgtr_dev - representation of a ZynMP GT device
257 return readl(gtr_dev->serdes + reg); in xpsgtr_read()
262 writel(value, gtr_dev->serdes + reg); in xpsgtr_write()
277 void __iomem *addr = gtr_phy->dev->serdes in xpsgtr_read_phy()
278 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_read_phy()
286 void __iomem *addr = gtr_phy->dev->serdes in xpsgtr_write_phy()
287 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_write_phy()
295 void __iomem *addr = gtr_phy->dev->serdes in xpsgtr_clr_set_phy()
296 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_clr_set_phy()
309 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_wait_pll_lock()
313 dev_dbg(gtr_dev->dev, "Waiting for PLL lock\n"); in xpsgtr_wait_pll_lock()
323 if (--timeout == 0) { in xpsgtr_wait_pll_lock()
324 ret = -ETIMEDOUT; in xpsgtr_wait_pll_lock()
331 if (ret == -ETIMEDOUT) in xpsgtr_wait_pll_lock()
332 dev_err(gtr_dev->dev, in xpsgtr_wait_pll_lock()
334 gtr_phy->lane, gtr_phy->type, gtr_phy->protocol); in xpsgtr_wait_pll_lock()
339 /* Configure PLL and spread-sprectrum clock. */
342 const struct xpsgtr_ssc *ssc; in xpsgtr_configure_pll() local
345 ssc = gtr_phy->dev->refclk_sscs[gtr_phy->refclk]; in xpsgtr_configure_pll()
346 step_size = ssc->step_size; in xpsgtr_configure_pll()
348 xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane), in xpsgtr_configure_pll()
349 PLL_FREQ_MASK, ssc->pll_ref_clk); in xpsgtr_configure_pll()
351 /* Enable lane clock sharing, if required */ in xpsgtr_configure_pll()
352 if (gtr_phy->refclk != gtr_phy->lane) { in xpsgtr_configure_pll()
354 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane), in xpsgtr_configure_pll()
355 L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk); in xpsgtr_configure_pll()
358 /* SSC step size [7:0] */ in xpsgtr_configure_pll()
362 /* SSC step size [15:8] */ in xpsgtr_configure_pll()
367 /* SSC step size [23:16] */ in xpsgtr_configure_pll()
372 /* SSC steps [7:0] */ in xpsgtr_configure_pll()
374 STEPS_0_MASK, ssc->steps & STEPS_0_MASK); in xpsgtr_configure_pll()
376 /* SSC steps [10:8] */ in xpsgtr_configure_pll()
379 (ssc->steps >> STEP_SIZE_SHIFT) & STEPS_1_MASK); in xpsgtr_configure_pll()
381 /* SSC step size [24:25] */ in xpsgtr_configure_pll()
391 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_lane_set_protocol()
392 u8 protocol = gtr_phy->protocol; in xpsgtr_lane_set_protocol()
394 switch (gtr_phy->lane) { in xpsgtr_lane_set_protocol()
422 /* DP-specific initialization. */
435 /* SATA-specific initialization. */
438 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_phy_init_sata()
442 writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET); in xpsgtr_phy_init_sata()
445 /* SGMII-specific initialization. */
448 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_phy_init_sgmii()
449 u32 mask = PROT_BUS_WIDTH_MASK(gtr_phy->lane); in xpsgtr_phy_init_sgmii()
450 u32 val = PROT_BUS_WIDTH_10 << PROT_BUS_WIDTH_SHIFT(gtr_phy->lane); in xpsgtr_phy_init_sgmii()
459 /* Configure TX de-emphasis and margining for DP. */
490 * except when gtr_phy->skip_phy_init is false (this happens when FPD is in xpsgtr_phy_init_required()
493 if (gtr_phy->protocol == ICM_PROTOCOL_USB && gtr_phy->skip_phy_init) in xpsgtr_phy_init_required()
506 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_phy_tx_term_fix()
529 dev_dbg(gtr_dev->dev, "calibrating...\n"); in xpsgtr_phy_tx_term_fix()
537 if (!--timeout) { in xpsgtr_phy_tx_term_fix()
538 dev_err(gtr_dev->dev, "calibration time out\n"); in xpsgtr_phy_tx_term_fix()
539 return -ETIMEDOUT; in xpsgtr_phy_tx_term_fix()
545 dev_dbg(gtr_dev->dev, "calibration done\n"); in xpsgtr_phy_tx_term_fix()
570 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_phy_init()
573 mutex_lock(>r_dev->gtr_mutex); in xpsgtr_phy_init()
575 /* Configure and enable the clock when peripheral phy_init call */ in xpsgtr_phy_init()
576 if (clk_prepare_enable(gtr_dev->clk[gtr_phy->lane])) in xpsgtr_phy_init()
583 if (gtr_dev->tx_term_fix) { in xpsgtr_phy_init()
588 gtr_dev->tx_term_fix = false; in xpsgtr_phy_init()
591 /* Enable coarse code saturation limiting logic. */ in xpsgtr_phy_init()
595 * Configure the PLL, the lane protocol, and perform protocol-specific in xpsgtr_phy_init()
601 switch (gtr_phy->protocol) { in xpsgtr_phy_init()
616 mutex_unlock(>r_dev->gtr_mutex); in xpsgtr_phy_init()
623 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_phy_exit()
625 gtr_phy->skip_phy_init = false; in xpsgtr_phy_exit()
628 clk_disable_unprepare(gtr_dev->clk[gtr_phy->lane]); in xpsgtr_phy_exit()
646 if (gtr_phy->protocol != ICM_PROTOCOL_DP || in xpsgtr_phy_power_on()
647 gtr_phy->type == XPSGTR_TYPE_DP_0) in xpsgtr_phy_power_on()
657 if (gtr_phy->protocol != ICM_PROTOCOL_DP) in xpsgtr_phy_configure()
660 xpsgtr_phy_configure_dp(gtr_phy, opts->dp.pre[0], opts->dp.voltage[0]); in xpsgtr_phy_configure()
693 gtr_phy->protocol = ICM_PROTOCOL_SATA; in xpsgtr_set_lane_type()
704 gtr_phy->protocol = ICM_PROTOCOL_USB; in xpsgtr_set_lane_type()
715 gtr_phy->protocol = ICM_PROTOCOL_DP; in xpsgtr_set_lane_type()
728 gtr_phy->protocol = ICM_PROTOCOL_PCIE; in xpsgtr_set_lane_type()
741 gtr_phy->protocol = ICM_PROTOCOL_SGMII; in xpsgtr_set_lane_type()
745 return -EINVAL; in xpsgtr_set_lane_type()
749 return -EINVAL; in xpsgtr_set_lane_type()
751 gtr_phy->type = phy_types[phy_instance]; in xpsgtr_set_lane_type()
782 if (args->args_count != 4) { in xpsgtr_xlate()
784 return ERR_PTR(-EINVAL); in xpsgtr_xlate()
791 phy_lane = args->args[0]; in xpsgtr_xlate()
792 if (phy_lane >= ARRAY_SIZE(gtr_dev->phys)) { in xpsgtr_xlate()
794 return ERR_PTR(-ENODEV); in xpsgtr_xlate()
797 gtr_phy = >r_dev->phys[phy_lane]; in xpsgtr_xlate()
798 phy_type = args->args[1]; in xpsgtr_xlate()
799 phy_instance = args->args[2]; in xpsgtr_xlate()
803 dev_err(gtr_dev->dev, "Invalid PHY type and/or instance\n"); in xpsgtr_xlate()
807 refclk = args->args[3]; in xpsgtr_xlate()
808 if (refclk >= ARRAY_SIZE(gtr_dev->refclk_sscs) || in xpsgtr_xlate()
809 !gtr_dev->refclk_sscs[refclk]) { in xpsgtr_xlate()
811 return ERR_PTR(-EINVAL); in xpsgtr_xlate()
814 gtr_phy->refclk = refclk; in xpsgtr_xlate()
821 if (icm_matrix[phy_lane][i] == gtr_phy->type) in xpsgtr_xlate()
822 return gtr_phy->phy; in xpsgtr_xlate()
825 return ERR_PTR(-EINVAL); in xpsgtr_xlate()
837 gtr_dev->saved_icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0); in xpsgtr_runtime_suspend()
838 gtr_dev->saved_icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1); in xpsgtr_runtime_suspend()
854 if (!gtr_dev->saved_icm_cfg0 && !gtr_dev->saved_icm_cfg1) in xpsgtr_runtime_resume()
858 if (icm_cfg0 == gtr_dev->saved_icm_cfg0 && in xpsgtr_runtime_resume()
859 icm_cfg1 == gtr_dev->saved_icm_cfg1) in xpsgtr_runtime_resume()
865 for (i = 0; i < ARRAY_SIZE(gtr_dev->phys); i++) in xpsgtr_runtime_resume()
866 gtr_dev->phys[i].skip_phy_init = skip_phy_init; in xpsgtr_runtime_resume()
881 for (refclk = 0; refclk < ARRAY_SIZE(gtr_dev->refclk_sscs); ++refclk) { in xpsgtr_get_ref_clocks()
888 clk = devm_clk_get_optional(gtr_dev->dev, name); in xpsgtr_get_ref_clocks()
890 return dev_err_probe(gtr_dev->dev, PTR_ERR(clk), in xpsgtr_get_ref_clocks()
898 gtr_dev->clk[refclk] = clk; in xpsgtr_get_ref_clocks()
901 * Get the spread spectrum (SSC) settings for the reference in xpsgtr_get_ref_clocks()
910 if (abs(rate - ssc_lookup[i].refclk_rate) < error) { in xpsgtr_get_ref_clocks()
911 gtr_dev->refclk_sscs[refclk] = &ssc_lookup[i]; in xpsgtr_get_ref_clocks()
917 dev_err(gtr_dev->dev, in xpsgtr_get_ref_clocks()
920 return -EINVAL; in xpsgtr_get_ref_clocks()
929 struct device_node *np = pdev->dev.of_node; in xpsgtr_probe()
935 gtr_dev = devm_kzalloc(&pdev->dev, sizeof(*gtr_dev), GFP_KERNEL); in xpsgtr_probe()
937 return -ENOMEM; in xpsgtr_probe()
939 gtr_dev->dev = &pdev->dev; in xpsgtr_probe()
942 mutex_init(>r_dev->gtr_mutex); in xpsgtr_probe()
944 if (of_device_is_compatible(np, "xlnx,zynqmp-psgtr")) in xpsgtr_probe()
945 gtr_dev->tx_term_fix = in xpsgtr_probe()
946 of_property_read_bool(np, "xlnx,tx-termination-fix"); in xpsgtr_probe()
949 gtr_dev->serdes = devm_platform_ioremap_resource_byname(pdev, "serdes"); in xpsgtr_probe()
950 if (IS_ERR(gtr_dev->serdes)) in xpsgtr_probe()
951 return PTR_ERR(gtr_dev->serdes); in xpsgtr_probe()
953 gtr_dev->siou = devm_platform_ioremap_resource_byname(pdev, "siou"); in xpsgtr_probe()
954 if (IS_ERR(gtr_dev->siou)) in xpsgtr_probe()
955 return PTR_ERR(gtr_dev->siou); in xpsgtr_probe()
962 for (port = 0; port < ARRAY_SIZE(gtr_dev->phys); ++port) { in xpsgtr_probe()
963 struct xpsgtr_phy *gtr_phy = >r_dev->phys[port]; in xpsgtr_probe()
966 gtr_phy->lane = port; in xpsgtr_probe()
967 gtr_phy->dev = gtr_dev; in xpsgtr_probe()
969 phy = devm_phy_create(&pdev->dev, np, &xpsgtr_phyops); in xpsgtr_probe()
971 dev_err(&pdev->dev, "failed to create PHY\n"); in xpsgtr_probe()
975 gtr_phy->phy = phy; in xpsgtr_probe()
980 provider = devm_of_phy_provider_register(&pdev->dev, xpsgtr_xlate); in xpsgtr_probe()
982 dev_err(&pdev->dev, "registering provider failed\n"); in xpsgtr_probe()
986 pm_runtime_set_active(gtr_dev->dev); in xpsgtr_probe()
987 pm_runtime_enable(gtr_dev->dev); in xpsgtr_probe()
989 ret = pm_runtime_resume_and_get(gtr_dev->dev); in xpsgtr_probe()
991 pm_runtime_disable(gtr_dev->dev); in xpsgtr_probe()
1002 pm_runtime_disable(gtr_dev->dev); in xpsgtr_remove()
1003 pm_runtime_put_noidle(gtr_dev->dev); in xpsgtr_remove()
1004 pm_runtime_set_suspended(gtr_dev->dev); in xpsgtr_remove()
1010 { .compatible = "xlnx,zynqmp-psgtr", },
1011 { .compatible = "xlnx,zynqmp-psgtr-v1.1", },
1020 .name = "xilinx-psgtr",