402 	ret = regmap_field_write(wiz->por_en, 0x1);  in wiz_reset()
408 	ret = regmap_field_write(wiz->por_en, 0x0);  in wiz_reset()
425 			ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1);  in wiz_p_mac_div_sel()
429 			ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2);  in wiz_p_mac_div_sel()
451 			ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3);  in wiz_mode_select()
452 			ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3);  in wiz_mode_select()
453 			ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x3);  in wiz_mode_select()
459 		ret = regmap_field_write(wiz->p_standard_mode[i], mode);  in wiz_mode_select()
474 		ret = regmap_field_write(wiz->p_align[i], enable);  in wiz_init_raw_interface()
478 		ret = regmap_field_write(wiz->p_raw_auto_start[i], enable);  in wiz_init_raw_interface()
711 	regmap_field_write(phy_en_refclk, 1);  in wiz_phy_en_refclk_enable()
721 	regmap_field_write(phy_en_refclk, 0);  in wiz_phy_en_refclk_disable()
800 	return regmap_field_write(field, val);  in wiz_clk_mux_set_parent()
956 	return regmap_field_write(field, val);  in wiz_clk_div_set_rate()
1100 		regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1);  in wiz_clock_init()
1102 		regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);  in wiz_clock_init()
1109 			regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x2);  in wiz_clock_init()
1112 			regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x3);  in wiz_clock_init()
1115 			regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0);  in wiz_clock_init()
1134 			regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1);  in wiz_clock_init()
1136 			regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3);  in wiz_clock_init()
1149 		regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);  in wiz_clock_init()
1151 		regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);  in wiz_clock_init()
1223 		ret = regmap_field_write(wiz->phy_reset_n, false);  in wiz_phy_reset_assert()
1227 	ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE);  in wiz_phy_reset_assert()
1236 			return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);  in wiz_phy_fullrt_div()
1244 			return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2);  in wiz_phy_fullrt_div()
1266 				regmap_field_write(wiz->typec_ln10_swap, 1);  in wiz_phy_reset_deassert()
1268 				regmap_field_write(wiz->typec_ln10_swap, 0);  in wiz_phy_reset_deassert()
1281 						regmap_field_write(wiz->typec_ln10_swap, 1);  in wiz_phy_reset_deassert()
1284 						regmap_field_write(wiz->typec_ln23_swap, 1);  in wiz_phy_reset_deassert()
1295 		ret = regmap_field_write(wiz->phy_reset_n, true);  in wiz_phy_reset_deassert()
1304 		ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);  in wiz_phy_reset_deassert()
1306 		ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);  in wiz_phy_reset_deassert()
1572 		regmap_field_write(wiz->sup_legacy_clk_override, 1);  in wiz_probe()