Lines Matching +full:0 +full:x5b

10 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL	0x720
11 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK	0x1
12 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN	BIT(0)
14 #define EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS	0x5e
18 	PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
19 	PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
20 	PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
21 	PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY),
22 	PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
23 	PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
24 	PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
25 	PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
26 	PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
27 	PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
28 	PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
29 	PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
30 	PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
31 	PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
37 	PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY),
38 	PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY),
39 	PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_HS_ANY),
40 	/* Setting order: 1st(0x16, 2nd(0x15) */
41 	PHY_COMN_REG_CFG(0x016, 0xff, PWR_MODE_HS_ANY),
42 	PHY_COMN_REG_CFG(0x015, 0x80, PWR_MODE_HS_ANY),
43 	PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_HS_ANY),
44 	PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_HS_ANY),
45 	PHY_TRSV_REG_CFG(0x037, 0x43, PWR_MODE_HS_ANY),
46 	PHY_TRSV_REG_CFG(0x038, 0x3f, PWR_MODE_HS_ANY),
47 	PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_HS_G2_SER_A),
48 	PHY_TRSV_REG_CFG(0x042, 0xbb, PWR_MODE_HS_G2_SER_B),
49 	PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_HS_ANY),
50 	PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_HS_ANY),
51 	PHY_TRSV_REG_CFG(0x034, 0x35, PWR_MODE_HS_G2_SER_A),
52 	PHY_TRSV_REG_CFG(0x034, 0x36, PWR_MODE_HS_G2_SER_B),
53 	PHY_TRSV_REG_CFG(0x035, 0x5b, PWR_MODE_HS_G2_SER_A),
54 	PHY_TRSV_REG_CFG(0x035, 0x5c, PWR_MODE_HS_G2_SER_B),
60 	PHY_COMN_REG_CFG(0x015, 0x00, PWR_MODE_HS_ANY),
61 	PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_HS_ANY),