246 	unsigned long pixclock;  member
251 	unsigned long pixclock;  member
611 							    inno->pixclock);  in inno_hdmi_phy_power_on()
636 	inno->plat_data->clk_ops->set_rate(&inno->hw, inno->pixclock, 24000000);  in inno_hdmi_phy_power_on()
682 	for (; cfg->pixclock != 0; cfg++)  in inno_hdmi_phy_get_pre_pll_cfg()
683 		if (cfg->pixclock == rate && cfg->tmdsclock == tmdsclock)  in inno_hdmi_phy_get_pre_pll_cfg()
686 	if (cfg->pixclock == 0)  in inno_hdmi_phy_get_pre_pll_cfg()
745 	inno->pixclock = vco;  in inno_hdmi_phy_rk3228_clk_recalc_rate()
747 	dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);  in inno_hdmi_phy_rk3228_clk_recalc_rate()
760 	for (; cfg->pixclock != 0; cfg++)  in inno_hdmi_phy_rk3228_clk_round_rate()
761 		if (cfg->pixclock == rate && !cfg->fracdiv)  in inno_hdmi_phy_rk3228_clk_round_rate()
764 	if (cfg->pixclock == 0)  in inno_hdmi_phy_rk3228_clk_round_rate()
767 	return cfg->pixclock;  in inno_hdmi_phy_rk3228_clk_round_rate()
783 	if (inno->pixclock == rate && inno->tmdsclock == tmdsclock)  in inno_hdmi_phy_rk3228_clk_set_rate()
827 	inno->pixclock = rate;  in inno_hdmi_phy_rk3228_clk_set_rate()
901 	inno->pixclock = DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000;  in inno_hdmi_phy_rk3328_clk_recalc_rate()
904 		__func__, inno->pixclock, vco);  in inno_hdmi_phy_rk3328_clk_recalc_rate()
906 	return inno->pixclock;  in inno_hdmi_phy_rk3328_clk_recalc_rate()
917 	for (; cfg->pixclock != 0; cfg++)  in inno_hdmi_phy_rk3328_clk_round_rate()
918 		if (cfg->pixclock == rate)  in inno_hdmi_phy_rk3328_clk_round_rate()
921 	if (cfg->pixclock == 0)  in inno_hdmi_phy_rk3328_clk_round_rate()
924 	return cfg->pixclock;  in inno_hdmi_phy_rk3328_clk_round_rate()
940 	if (inno->pixclock == rate && inno->tmdsclock == tmdsclock)  in inno_hdmi_phy_rk3328_clk_set_rate()
981 	inno->pixclock = rate;  in inno_hdmi_phy_rk3328_clk_set_rate()