Lines Matching +full:0 +full:x1fc

9 #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX		0x30
10 #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX		0x34
11 #define QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN			0xac
12 #define QSERDES_V6_20_TX_LANE_MODE_1				0x78
13 #define QSERDES_V6_20_TX_LANE_MODE_2				0x7c
14 #define QSERDES_V6_20_TX_LANE_MODE_3				0x80
16 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2			0x08
17 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3			0x0c
18 #define QSERDES_V6_20_RX_UCDR_PI_CONTROLS			0x20
19 #define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3		0x34
20 #define QSERDES_V6_20_RX_IVCM_CAL_CTRL2				0x9c
21 #define QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET			0xa0
22 #define QSERDES_V6_20_RX_DFE_3					0xb4
23 #define QSERDES_V6_20_RX_VGA_CAL_MAN_VAL			0xe8
24 #define QSERDES_V6_20_RX_GM_CAL					0x10c
25 #define QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4			0x120
26 #define QSERDES_V6_20_RX_SIGDET_ENABLES				0x148
27 #define QSERDES_V6_20_RX_PHPRE_CTRL				0x188
28 #define QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET		0x194
29 #define QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32		0x1dc
30 #define QSERDES_V6_20_RX_MODE_RATE2_B0				0x1f4
31 #define QSERDES_V6_20_RX_MODE_RATE2_B1				0x1f8
32 #define QSERDES_V6_20_RX_MODE_RATE2_B2				0x1fc
33 #define QSERDES_V6_20_RX_MODE_RATE2_B3				0x200
34 #define QSERDES_V6_20_RX_MODE_RATE2_B4				0x204
35 #define QSERDES_V6_20_RX_MODE_RATE2_B5				0x208
36 #define QSERDES_V6_20_RX_MODE_RATE2_B6				0x20c
37 #define QSERDES_V6_20_RX_MODE_RATE3_B0				0x210
38 #define QSERDES_V6_20_RX_MODE_RATE3_B1				0x214
39 #define QSERDES_V6_20_RX_MODE_RATE3_B2				0x218
40 #define QSERDES_V6_20_RX_MODE_RATE3_B3				0x21c
41 #define QSERDES_V6_20_RX_MODE_RATE3_B4				0x220
42 #define QSERDES_V6_20_RX_MODE_RATE3_B5				0x224
43 #define QSERDES_V6_20_RX_MODE_RATE3_B6				0x228