Lines Matching +full:src +full:- +full:ref +full:- +full:clk +full:- +full:mhz
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
27 * The Ref PLL CMU CSR (Configuration System Registers) is accessed
33 * The Ref PLL CMU can be located within the same PHY IP or outside the PHY IP
34 * due to shared Ref PLL CMU. For PHY with Ref PLL CMU shared with another IP,
37 * to located the SDS/Ref PLL CMU module and its clock for that IP enabled.
47 #include <linux/clk.h>
86 #define SATA_MEM_RESET_RD(src) (((src) & 0x00000020) >> 5) argument
95 #define REGSPEC_CFG_I_TX_WORDMODE0_SET(dst, src) \ argument
96 (((dst) & ~0x00070000) | (((u32) (src) << 16) & 0x00070000))
97 #define REGSPEC_CFG_I_RX_WORDMODE0_SET(dst, src) \ argument
98 (((dst) & ~0x00e00000) | (((u32) (src) << 21) & 0x00e00000))
100 #define REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(dst, src) \ argument
101 (((dst) & ~0x00007fff) | (((u32) (src)) & 0x00007fff))
103 #define CFG_I_SPD_SEL_CDR_OVR1_SET(dst, src) \ argument
104 (((dst) & ~0x0000000f) | (((u32) (src)) & 0x0000000f))
110 #define CFG_IND_ADDR_SET(dst, src) \ argument
111 (((dst) & ~0x003ffff0) | (((u32) (src) << 4) & 0x003ffff0))
115 #define I_RESET_B_SET(dst, src) \ argument
116 (((dst) & ~0x00000001) | (((u32) (src)) & 0x00000001))
117 #define I_PLL_FBDIV_SET(dst, src) \ argument
118 (((dst) & ~0x001ff000) | (((u32) (src) << 12) & 0x001ff000))
119 #define I_CUSTOMEROV_SET(dst, src) \ argument
120 (((dst) & ~0x00000f80) | (((u32) (src) << 7) & 0x00000f80))
121 #define O_PLL_LOCK_RD(src) (((src) & 0x40000000) >> 30) argument
122 #define O_PLL_READY_RD(src) (((src) & 0x80000000) >> 31) argument
127 #define CMU_REG0_PLL_REF_SEL_SET(dst, src) \ argument
128 (((dst) & ~0x00002000) | (((u32) (src) << 13) & 0x00002000))
130 #define CMU_REG0_CAL_COUNT_RESOL_SET(dst, src) \ argument
131 (((dst) & ~0x000000e0) | (((u32) (src) << 5) & 0x000000e0))
133 #define CMU_REG1_PLL_CP_SET(dst, src) \ argument
134 (((dst) & ~0x00003c00) | (((u32) (src) << 10) & 0x00003c00))
135 #define CMU_REG1_PLL_MANUALCAL_SET(dst, src) \ argument
136 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
137 #define CMU_REG1_PLL_CP_SEL_SET(dst, src) \ argument
138 (((dst) & ~0x000003e0) | (((u32) (src) << 5) & 0x000003e0))
140 #define CMU_REG1_REFCLK_CMOS_SEL_SET(dst, src) \ argument
141 (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
143 #define CMU_REG2_PLL_REFDIV_SET(dst, src) \ argument
144 (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
145 #define CMU_REG2_PLL_LFRES_SET(dst, src) \ argument
146 (((dst) & ~0x0000001e) | (((u32) (src) << 1) & 0x0000001e))
147 #define CMU_REG2_PLL_FBDIV_SET(dst, src) \ argument
148 (((dst) & ~0x00003fe0) | (((u32) (src) << 5) & 0x00003fe0))
150 #define CMU_REG3_VCOVARSEL_SET(dst, src) \ argument
151 (((dst) & ~0x0000000f) | (((u32) (src) << 0) & 0x0000000f))
152 #define CMU_REG3_VCO_MOMSEL_INIT_SET(dst, src) \ argument
153 (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
154 #define CMU_REG3_VCO_MANMOMSEL_SET(dst, src) \ argument
155 (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
158 #define CMU_REG5_PLL_LFSMCAP_SET(dst, src) \ argument
159 (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
160 #define CMU_REG5_PLL_LOCK_RESOLUTION_SET(dst, src) \ argument
161 (((dst) & ~0x0000000e) | (((u32) (src) << 1) & 0x0000000e))
162 #define CMU_REG5_PLL_LFCAP_SET(dst, src) \ argument
163 (((dst) & ~0x00003000) | (((u32) (src) << 12) & 0x00003000))
166 #define CMU_REG6_PLL_VREGTRIM_SET(dst, src) \ argument
167 (((dst) & ~0x00000600) | (((u32) (src) << 9) & 0x00000600))
168 #define CMU_REG6_MAN_PVT_CAL_SET(dst, src) \ argument
169 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
171 #define CMU_REG7_PLL_CALIB_DONE_RD(src) ((0x00004000 & (u32) (src)) >> 14) argument
172 #define CMU_REG7_VCO_CAL_FAIL_RD(src) ((0x00000c00 & (u32) (src)) >> 10) argument
183 #define CMU_REG9_TX_WORD_MODE_CH1_SET(dst, src) \ argument
184 (((dst) & ~0x00000380) | (((u32) (src) << 7) & 0x00000380))
185 #define CMU_REG9_TX_WORD_MODE_CH0_SET(dst, src) \ argument
186 (((dst) & ~0x00000070) | (((u32) (src) << 4) & 0x00000070))
187 #define CMU_REG9_PLL_POST_DIVBY2_SET(dst, src) \ argument
188 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
189 #define CMU_REG9_VBG_BYPASSB_SET(dst, src) \ argument
190 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
191 #define CMU_REG9_IGEN_BYPASS_SET(dst, src) \ argument
192 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
194 #define CMU_REG10_VREG_REFSEL_SET(dst, src) \ argument
195 (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
198 #define CMU_REG12_STATE_DELAY9_SET(dst, src) \ argument
199 (((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0))
206 #define CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(dst, src) \ argument
207 (((dst) & ~0x0000001c) | (((u32) (src) << 2) & 0x0000001c))
208 #define CMU_REG16_CALIBRATION_DONE_OVERRIDE_SET(dst, src) \ argument
209 (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
210 #define CMU_REG16_BYPASS_PLL_LOCK_SET(dst, src) \ argument
211 (((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020))
213 #define CMU_REG17_PVT_CODE_R2A_SET(dst, src) \ argument
214 (((dst) & ~0x00007f00) | (((u32) (src) << 8) & 0x00007f00))
215 #define CMU_REG17_RESERVED_7_SET(dst, src) \ argument
216 (((dst) & ~0x000000e0) | (((u32) (src) << 5) & 0x000000e0))
227 #define CMU_REG26_FORCE_PLL_LOCK_SET(dst, src) \ argument
228 (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
233 #define CMU_REG30_LOCK_COUNT_SET(dst, src) \ argument
234 (((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006))
235 #define CMU_REG30_PCIE_MODE_SET(dst, src) \ argument
236 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
240 #define CMU_REG32_PVT_CAL_WAIT_SEL_SET(dst, src) \ argument
241 (((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006))
242 #define CMU_REG32_IREF_ADJ_SET(dst, src) \ argument
243 (((dst) & ~0x00000180) | (((u32) (src) << 7) & 0x00000180))
246 #define CMU_REG34_VCO_CAL_VTH_LO_MAX_SET(dst, src) \ argument
247 (((dst) & ~0x0000000f) | (((u32) (src) << 0) & 0x0000000f))
248 #define CMU_REG34_VCO_CAL_VTH_HI_MAX_SET(dst, src) \ argument
249 (((dst) & ~0x00000f00) | (((u32) (src) << 8) & 0x00000f00))
250 #define CMU_REG34_VCO_CAL_VTH_LO_MIN_SET(dst, src) \ argument
251 (((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0))
252 #define CMU_REG34_VCO_CAL_VTH_HI_MIN_SET(dst, src) \ argument
253 (((dst) & ~0x0000f000) | (((u32) (src) << 12) & 0x0000f000))
255 #define CMU_REG35_PLL_SSC_MOD_SET(dst, src) \ argument
256 (((dst) & ~0x0000fe00) | (((u32) (src) << 9) & 0x0000fe00))
258 #define CMU_REG36_PLL_SSC_EN_SET(dst, src) \ argument
259 (((dst) & ~0x00000010) | (((u32) (src) << 4) & 0x00000010))
260 #define CMU_REG36_PLL_SSC_VSTEP_SET(dst, src) \ argument
261 (((dst) & ~0x0000ffc0) | (((u32) (src) << 6) & 0x0000ffc0))
262 #define CMU_REG36_PLL_SSC_DSMSEL_SET(dst, src) \ argument
263 (((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020))
270 #define RXTX_REG0_CTLE_EQ_HR_SET(dst, src) \ argument
271 (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
272 #define RXTX_REG0_CTLE_EQ_QR_SET(dst, src) \ argument
273 (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
274 #define RXTX_REG0_CTLE_EQ_FR_SET(dst, src) \ argument
275 (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
277 #define RXTX_REG1_RXACVCM_SET(dst, src) \ argument
278 (((dst) & ~0x0000f000) | (((u32) (src) << 12) & 0x0000f000))
279 #define RXTX_REG1_CTLE_EQ_SET(dst, src) \ argument
280 (((dst) & ~0x00000f80) | (((u32) (src) << 7) & 0x00000f80))
281 #define RXTX_REG1_RXVREG1_SET(dst, src) \ argument
282 (((dst) & ~0x00000060) | (((u32) (src) << 5) & 0x00000060))
283 #define RXTX_REG1_RXIREF_ADJ_SET(dst, src) \ argument
284 (((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006))
286 #define RXTX_REG2_VTT_ENA_SET(dst, src) \ argument
287 (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
288 #define RXTX_REG2_TX_FIFO_ENA_SET(dst, src) \ argument
289 (((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020))
290 #define RXTX_REG2_VTT_SEL_SET(dst, src) \ argument
291 (((dst) & ~0x000000c0) | (((u32) (src) << 6) & 0x000000c0))
294 #define RXTX_REG4_TX_DATA_RATE_SET(dst, src) \ argument
295 (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
296 #define RXTX_REG4_TX_WORD_MODE_SET(dst, src) \ argument
297 (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
299 #define RXTX_REG5_TX_CN1_SET(dst, src) \ argument
300 (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
301 #define RXTX_REG5_TX_CP1_SET(dst, src) \ argument
302 (((dst) & ~0x000007e0) | (((u32) (src) << 5) & 0x000007e0))
303 #define RXTX_REG5_TX_CN2_SET(dst, src) \ argument
304 (((dst) & ~0x0000001f) | (((u32) (src) << 0) & 0x0000001f))
306 #define RXTX_REG6_TXAMP_CNTL_SET(dst, src) \ argument
307 (((dst) & ~0x00000780) | (((u32) (src) << 7) & 0x00000780))
308 #define RXTX_REG6_TXAMP_ENA_SET(dst, src) \ argument
309 (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
310 #define RXTX_REG6_RX_BIST_ERRCNT_RD_SET(dst, src) \ argument
311 (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
312 #define RXTX_REG6_TX_IDLE_SET(dst, src) \ argument
313 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
314 #define RXTX_REG6_RX_BIST_RESYNC_SET(dst, src) \ argument
315 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
319 #define RXTX_REG7_BIST_ENA_RX_SET(dst, src) \ argument
320 (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
321 #define RXTX_REG7_RX_WORD_MODE_SET(dst, src) \ argument
322 (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
324 #define RXTX_REG8_CDR_LOOP_ENA_SET(dst, src) \ argument
325 (((dst) & ~0x00004000) | (((u32) (src) << 14) & 0x00004000))
326 #define RXTX_REG8_CDR_BYPASS_RXLOS_SET(dst, src) \ argument
327 (((dst) & ~0x00000800) | (((u32) (src) << 11) & 0x00000800))
328 #define RXTX_REG8_SSC_ENABLE_SET(dst, src) \ argument
329 (((dst) & ~0x00000200) | (((u32) (src) << 9) & 0x00000200))
330 #define RXTX_REG8_SD_VREF_SET(dst, src) \ argument
331 (((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0))
332 #define RXTX_REG8_SD_DISABLE_SET(dst, src) \ argument
333 (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
335 #define RXTX_REG7_RESETB_RXD_SET(dst, src) \ argument
336 (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
337 #define RXTX_REG7_RESETB_RXA_SET(dst, src) \ argument
338 (((dst) & ~0x00000080) | (((u32) (src) << 7) & 0x00000080))
340 #define RXTX_REG7_LOOP_BACK_ENA_CTLE_SET(dst, src) \ argument
341 (((dst) & ~0x00004000) | (((u32) (src) << 14) & 0x00004000))
343 #define RXTX_REG11_PHASE_ADJUST_LIMIT_SET(dst, src) \ argument
344 (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
346 #define RXTX_REG12_LATCH_OFF_ENA_SET(dst, src) \ argument
347 (((dst) & ~0x00002000) | (((u32) (src) << 13) & 0x00002000))
348 #define RXTX_REG12_SUMOS_ENABLE_SET(dst, src) \ argument
349 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
351 #define RXTX_REG12_RX_DET_TERM_ENABLE_SET(dst, src) \ argument
352 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
355 #define RXTX_REG14_CLTE_LATCAL_MAN_PROG_SET(dst, src) \ argument
356 (((dst) & ~0x0000003f) | (((u32) (src) << 0) & 0x0000003f))
357 #define RXTX_REG14_CTLE_LATCAL_MAN_ENA_SET(dst, src) \ argument
358 (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
360 #define RXTX_REG26_PERIOD_ERROR_LATCH_SET(dst, src) \ argument
361 (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
362 #define RXTX_REG26_BLWC_ENA_SET(dst, src) \ argument
363 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
365 #define RXTX_REG21_DO_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10) argument
366 #define RXTX_REG21_XO_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4) argument
367 #define RXTX_REG21_LATCH_CAL_FAIL_ODD_RD(src) ((0x0000000f & (u32)(src))) argument
369 #define RXTX_REG22_SO_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4) argument
370 #define RXTX_REG22_EO_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10) argument
371 #define RXTX_REG22_LATCH_CAL_FAIL_EVEN_RD(src) ((0x0000000f & (u32)(src))) argument
373 #define RXTX_REG23_DE_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10) argument
374 #define RXTX_REG23_XE_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4) argument
376 #define RXTX_REG24_EE_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10) argument
377 #define RXTX_REG24_SE_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4) argument
382 #define RXTX_REG38_CUSTOMER_PINMODE_INV_SET(dst, src) \ argument
383 (((dst) & 0x0000fffe) | (((u32) (src) << 1) & 0x0000fffe))
402 #define RXTX_REG61_ISCAN_INBERT_SET(dst, src) \ argument
403 (((dst) & ~0x00000010) | (((u32) (src) << 4) & 0x00000010))
404 #define RXTX_REG61_LOADFREQ_SHIFT_SET(dst, src) \ argument
405 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
406 #define RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET(dst, src) \ argument
407 (((dst) & ~0x000000c0) | (((u32) (src) << 6) & 0x000000c0))
408 #define RXTX_REG61_SPD_SEL_CDR_SET(dst, src) \ argument
409 (((dst) & ~0x00003c00) | (((u32) (src) << 10) & 0x00003c00))
411 #define RXTX_REG62_PERIOD_H1_QLATCH_SET(dst, src) \ argument
412 (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
414 #define RXTX_REG89_MU_TH7_SET(dst, src) \ argument
415 (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
416 #define RXTX_REG89_MU_TH8_SET(dst, src) \ argument
417 (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
418 #define RXTX_REG89_MU_TH9_SET(dst, src) \ argument
419 (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
421 #define RXTX_REG96_MU_FREQ1_SET(dst, src) \ argument
422 (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
423 #define RXTX_REG96_MU_FREQ2_SET(dst, src) \ argument
424 (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
425 #define RXTX_REG96_MU_FREQ3_SET(dst, src) \ argument
426 (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
428 #define RXTX_REG99_MU_PHASE1_SET(dst, src) \ argument
429 (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
430 #define RXTX_REG99_MU_PHASE2_SET(dst, src) \ argument
431 (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
432 #define RXTX_REG99_MU_PHASE3_SET(dst, src) \ argument
433 (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
435 #define RXTX_REG102_FREQLOOP_LIMIT_SET(dst, src) \ argument
436 (((dst) & ~0x00000060) | (((u32) (src) << 5) & 0x00000060))
439 #define RXTX_REG121_SUMOS_CAL_CODE_RD(src) ((0x0000003e & (u32)(src)) >> 0x1) argument
441 #define RXTX_REG125_PQ_REG_SET(dst, src) \ argument
442 (((dst) & ~0x0000fe00) | (((u32) (src) << 9) & 0x0000fe00))
443 #define RXTX_REG125_SIGN_PQ_SET(dst, src) \ argument
444 (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
445 #define RXTX_REG125_SIGN_PQ_2C_SET(dst, src) \ argument
446 (((dst) & ~0x00000080) | (((u32) (src) << 7) & 0x00000080))
447 #define RXTX_REG125_PHZ_MANUALCODE_SET(dst, src) \ argument
448 (((dst) & ~0x0000007c) | (((u32) (src) << 2) & 0x0000007c))
449 #define RXTX_REG125_PHZ_MANUAL_SET(dst, src) \ argument
450 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
454 #define RXTX_REG127_FORCE_SUM_CAL_START_SET(dst, src) \ argument
455 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
456 #define RXTX_REG127_FORCE_LAT_CAL_START_SET(dst, src) \ argument
457 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
458 #define RXTX_REG127_LATCH_MAN_CAL_ENA_SET(dst, src) \ argument
459 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
460 #define RXTX_REG127_DO_LATCH_MANCAL_SET(dst, src) \ argument
461 (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
462 #define RXTX_REG127_XO_LATCH_MANCAL_SET(dst, src) \ argument
463 (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
465 #define RXTX_REG128_LATCH_CAL_WAIT_SEL_SET(dst, src) \ argument
466 (((dst) & ~0x0000000c) | (((u32) (src) << 2) & 0x0000000c))
467 #define RXTX_REG128_EO_LATCH_MANCAL_SET(dst, src) \ argument
468 (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
469 #define RXTX_REG128_SO_LATCH_MANCAL_SET(dst, src) \ argument
470 (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
472 #define RXTX_REG129_DE_LATCH_MANCAL_SET(dst, src) \ argument
473 (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
474 #define RXTX_REG129_XE_LATCH_MANCAL_SET(dst, src) \ argument
475 (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
477 #define RXTX_REG130_EE_LATCH_MANCAL_SET(dst, src) \ argument
478 (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
479 #define RXTX_REG130_SE_LATCH_MANCAL_SET(dst, src) \ argument
480 (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
482 #define RXTX_REG145_TX_IDLE_SATA_SET(dst, src) \ argument
483 (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
484 #define RXTX_REG145_RXES_ENA_SET(dst, src) \ argument
485 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
486 #define RXTX_REG145_RXDFE_CONFIG_SET(dst, src) \ argument
487 (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
488 #define RXTX_REG145_RXVWES_LATENA_SET(dst, src) \ argument
489 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
526 u32 txprecursor_cn1[MAX_LANE*3]; /* Tx emphasis taps 1st pre-cursor */
527 u32 txprecursor_cn2[MAX_LANE*3]; /* Tx emphasis taps 2nd pre-cursor */
528 u32 txpostcursor_cp1[MAX_LANE*3]; /* Tx emphasis taps post-cursor */
537 struct clk *clk; /* Optional clock */ member
548 MODULE_PARM_DESC(preA3Chip, "Enable pre-A3 chip support (1=enable 0=disable)");
597 void __iomem *sds_base = ctx->sds_base; in cmu_wr()
608 pr_debug("CMU WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, val); in cmu_wr()
614 void __iomem *sds_base = ctx->sds_base; in cmu_rd()
660 void __iomem *sds_base = ctx->sds_base; in serdes_wr()
669 pr_debug("SERDES WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, in serdes_wr()
675 void __iomem *sds_base = ctx->sds_base; in serdes_rd()
728 dev_dbg(ctx->dev, "Set external reference clock\n"); in xgene_phy_cfg_cmu_clk_type()
738 dev_dbg(ctx->dev, "Set internal reference clock\n"); in xgene_phy_cfg_cmu_clk_type()
753 dev_dbg(ctx->dev, in xgene_phy_cfg_cmu_clk_type()
799 /* Configure the PLL for either 100MHz or 50MHz */ in xgene_phy_sata_cfg_cmu_core()
856 /* Configure lane for 20-bits */ in xgene_phy_sata_cfg_cmu_core()
960 ctx->sata_param.txboostgain[lane * 3 + in xgene_phy_sata_cfg_lanes()
961 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
973 /* Configure Tx for 20-bits */ in xgene_phy_sata_cfg_lanes()
985 /* Set pre-emphasis first 1 and 2, and post-emphasis values */ in xgene_phy_sata_cfg_lanes()
988 ctx->sata_param.txprecursor_cn1[lane * 3 + in xgene_phy_sata_cfg_lanes()
989 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
991 ctx->sata_param.txpostcursor_cp1[lane * 3 + in xgene_phy_sata_cfg_lanes()
992 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
994 ctx->sata_param.txprecursor_cn2[lane * 3 + in xgene_phy_sata_cfg_lanes()
995 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1001 ctx->sata_param.txamplitude[lane * 3 + in xgene_phy_sata_cfg_lanes()
1002 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1009 /* Configure Rx for 20-bits */ in xgene_phy_sata_cfg_lanes()
1047 /* Set Eye Monitor counter width to 12-bit */ in xgene_phy_sata_cfg_lanes()
1096 ctx->sata_param.txeyedirection[lane * 3 + in xgene_phy_sata_cfg_lanes()
1097 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1099 ctx->sata_param.txeyetuning[lane * 3 + in xgene_phy_sata_cfg_lanes()
1100 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1139 void __iomem *csr_serdes = ctx->sds_base; in xgene_phy_cal_rdy_chk()
1188 * The serial transmit pins, TXP/TXN, have Pull-UP and Pull-DOWN in xgene_phy_cal_rdy_chk()
1218 } while (--loop > 0); in xgene_phy_cal_rdy_chk()
1221 dev_dbg(ctx->dev, "PLL calibration %s\n", in xgene_phy_cal_rdy_chk()
1224 dev_err(ctx->dev, in xgene_phy_cal_rdy_chk()
1226 return -1; in xgene_phy_cal_rdy_chk()
1228 dev_dbg(ctx->dev, "PLL calibration successful\n"); in xgene_phy_cal_rdy_chk()
1231 dev_dbg(ctx->dev, "PHY Tx is %sready\n", val & 0x300 ? "" : "not "); in xgene_phy_cal_rdy_chk()
1241 dev_dbg(ctx->dev, "Reset VCO and re-start again\n"); in xgene_phy_pdwn_force_vco()
1256 void __iomem *sds_base = ctx->sds_base; in xgene_phy_hw_init_sata()
1261 dev_dbg(ctx->dev, "Reset PHY\n"); in xgene_phy_hw_init_sata()
1275 ctx->sata_param.txspeed[ctx->sata_param.speed[0]]); in xgene_phy_hw_init_sata()
1278 dev_dbg(ctx->dev, "Set the customer pin mode to SATA\n"); in xgene_phy_hw_init_sata()
1296 /* Set Rx/Tx 20-bit */ in xgene_phy_hw_init_sata()
1309 } while (--i > 0); in xgene_phy_hw_init_sata()
1312 dev_err(ctx->dev, "PLL calibration failed\n"); in xgene_phy_hw_init_sata()
1323 dev_dbg(ctx->dev, "PHY init clk type %d\n", clk_type); in xgene_phy_hw_initialize()
1325 if (ctx->mode == MODE_SATA) { in xgene_phy_hw_initialize()
1330 dev_err(ctx->dev, "Un-supported customer pin mode %d\n", in xgene_phy_hw_initialize()
1331 ctx->mode); in xgene_phy_hw_initialize()
1332 return -ENODEV; in xgene_phy_hw_initialize()
1341 * Calibrate the receiver signal path offset in two steps - summar and
1438 dev_dbg(ctx->dev, "Generating avg calibration value for lane %d\n", in xgene_phy_gen_avg_val()
1441 /* Enable RX Hi-Z termination */ in xgene_phy_gen_avg_val()
1451 * Calibrate the receiver signal path offset in two steps - summar in xgene_phy_gen_avg_val()
1494 dev_dbg(ctx->dev, "Iteration %d:\n", avg_loop); in xgene_phy_gen_avg_val()
1495 dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n", in xgene_phy_gen_avg_val()
1498 dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n", in xgene_phy_gen_avg_val()
1501 dev_dbg(ctx->dev, "SUM 0x%x\n", sum_cal_itr); in xgene_phy_gen_avg_val()
1504 dev_err(ctx->dev, in xgene_phy_gen_avg_val()
1546 dev_dbg(ctx->dev, "Average Value:\n"); in xgene_phy_gen_avg_val()
1547 dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n", in xgene_phy_gen_avg_val()
1552 dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n", in xgene_phy_gen_avg_val()
1557 dev_dbg(ctx->dev, "SUM 0x%x\n", in xgene_phy_gen_avg_val()
1563 dev_dbg(ctx->dev, "Enable Manual Summer calibration\n"); in xgene_phy_gen_avg_val()
1567 dev_dbg(ctx->dev, "Enable Manual Latch calibration\n"); in xgene_phy_gen_avg_val()
1570 /* Disable RX Hi-Z termination */ in xgene_phy_gen_avg_val()
1588 dev_err(ctx->dev, "PHY initialize failed %d\n", rc); in xgene_phy_hw_init()
1593 if (!IS_ERR(ctx->clk)) { in xgene_phy_hw_init()
1595 clk_prepare_enable(ctx->clk); in xgene_phy_hw_init()
1596 clk_disable_unprepare(ctx->clk); in xgene_phy_hw_init()
1597 clk_prepare_enable(ctx->clk); in xgene_phy_hw_init()
1604 dev_dbg(ctx->dev, "PHY initialized\n"); in xgene_phy_hw_init()
1618 if (args->args_count <= 0) in xgene_phy_xlate()
1619 return ERR_PTR(-EINVAL); in xgene_phy_xlate()
1620 if (args->args[0] >= MODE_MAX) in xgene_phy_xlate()
1621 return ERR_PTR(-EINVAL); in xgene_phy_xlate()
1623 ctx->mode = args->args[0]; in xgene_phy_xlate()
1624 return ctx->phy; in xgene_phy_xlate()
1634 if (!of_property_read_u32_array(pdev->dev.of_node, name, buffer, in xgene_phy_get_param()
1659 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); in xgene_phy_probe()
1661 return -ENOMEM; in xgene_phy_probe()
1663 ctx->dev = &pdev->dev; in xgene_phy_probe()
1665 ctx->sds_base = devm_platform_ioremap_resource(pdev, 0); in xgene_phy_probe()
1666 if (IS_ERR(ctx->sds_base)) in xgene_phy_probe()
1667 return PTR_ERR(ctx->sds_base); in xgene_phy_probe()
1670 ctx->clk = clk_get(&pdev->dev, NULL); in xgene_phy_probe()
1673 xgene_phy_get_param(pdev, "apm,tx-eye-tuning", in xgene_phy_probe()
1674 ctx->sata_param.txeyetuning, 6, default_txeye_tuning, 1); in xgene_phy_probe()
1675 xgene_phy_get_param(pdev, "apm,tx-eye-direction", in xgene_phy_probe()
1676 ctx->sata_param.txeyedirection, 6, default_txeye_direction, 1); in xgene_phy_probe()
1677 xgene_phy_get_param(pdev, "apm,tx-boost-gain", in xgene_phy_probe()
1678 ctx->sata_param.txboostgain, 6, default_txboost_gain, 1); in xgene_phy_probe()
1679 xgene_phy_get_param(pdev, "apm,tx-amplitude", in xgene_phy_probe()
1680 ctx->sata_param.txamplitude, 6, default_txamp, 13300); in xgene_phy_probe()
1681 xgene_phy_get_param(pdev, "apm,tx-pre-cursor1", in xgene_phy_probe()
1682 ctx->sata_param.txprecursor_cn1, 6, default_txcn1, 18200); in xgene_phy_probe()
1683 xgene_phy_get_param(pdev, "apm,tx-pre-cursor2", in xgene_phy_probe()
1684 ctx->sata_param.txprecursor_cn2, 6, default_txcn2, 18200); in xgene_phy_probe()
1685 xgene_phy_get_param(pdev, "apm,tx-post-cursor", in xgene_phy_probe()
1686 ctx->sata_param.txpostcursor_cp1, 6, default_txcp1, 18200); in xgene_phy_probe()
1687 xgene_phy_get_param(pdev, "apm,tx-speed", in xgene_phy_probe()
1688 ctx->sata_param.txspeed, 3, default_spd, 1); in xgene_phy_probe()
1690 ctx->sata_param.speed[i] = 2; /* Default to Gen3 */ in xgene_phy_probe()
1694 ctx->phy = devm_phy_create(ctx->dev, NULL, &xgene_phy_ops); in xgene_phy_probe()
1695 if (IS_ERR(ctx->phy)) { in xgene_phy_probe()
1696 dev_dbg(&pdev->dev, "Failed to create PHY\n"); in xgene_phy_probe()
1697 return PTR_ERR(ctx->phy); in xgene_phy_probe()
1699 phy_set_drvdata(ctx->phy, ctx); in xgene_phy_probe()
1701 phy_provider = devm_of_phy_provider_register(ctx->dev, xgene_phy_xlate); in xgene_phy_probe()
1706 {.compatible = "apm,xgene-phy",},
1714 .name = "xgene-phy",
1720 MODULE_DESCRIPTION("APM X-Gene Multi-Purpose PHY driver");