Lines Matching +full:0 +full:x408000
31 #define SPX5_SERDES_QUIET_MODE_VAL 0x01ef4e0c
34 SPX5_SD10G28_CMU_MAIN = 0,
353 .cfg_en_adv = 0,
355 .cfg_en_dly = 0,
356 .cfg_tap_adv_3_0 = 0,
358 .cfg_tap_dly_4_0 = 0,
359 .cfg_eq_c_force_3_0 = 0xf,
368 .cfg_tap_adv_3_0 = 0,
370 .cfg_tap_dly_4_0 = 0x10,
371 .cfg_eq_c_force_3_0 = 0xf,
374 .cfg_alos_thr_2_0 = 0,
377 .cfg_en_adv = 0,
379 .cfg_en_dly = 0,
380 .cfg_tap_adv_3_0 = 0,
382 .cfg_tap_dly_4_0 = 0,
383 .cfg_eq_c_force_3_0 = 0xf,
385 .cfg_eq_r_force_3_0 = 0xc,
386 .cfg_alos_thr_2_0 = 0,
393 .tx_pre_div = 0,
394 .fifo_ck_div = 0,
396 .vco_div_mode = 0,
399 .subrate = 0,
400 .com_txcal_en = 0,
401 .com_tx_reserve_msb = (0x26 << 1),
402 .com_tx_reserve_lsb = 0xf0,
403 .cfg_itx_ipcml_base = 0,
404 .tx_reserve_msb = 0xcc,
405 .tx_reserve_lsb = 0xfe,
407 .rxterm = 0,
409 .dfe_tap = 0x1f,
413 .cfg_pi_bw_3_0 = 0,
415 .tx_tap_adv = 0xc,
419 .tx_pre_div = 0,
421 .pre_divsel = 0,
424 .ck_bitwidth = 0,
425 .subrate = 0,
427 .com_tx_reserve_msb = (0x20 << 1),
428 .com_tx_reserve_lsb = 0x40,
429 .cfg_itx_ipcml_base = 0,
430 .tx_reserve_msb = 0x4c,
431 .tx_reserve_lsb = 0x44,
433 .cfg_pi_bw_3_0 = 0,
436 .dfe_tap = 0x1f,
437 .txmargin = 0,
440 .tx_tap_dly = 0,
441 .tx_tap_adv = 0,
445 .tx_pre_div = 0,
447 .pre_divsel = 0,
450 .ck_bitwidth = 0,
451 .subrate = 0,
453 .com_tx_reserve_msb = (0x20 << 1),
454 .com_tx_reserve_lsb = 0,
455 .cfg_itx_ipcml_base = 0,
456 .tx_reserve_msb = 0xe,
457 .tx_reserve_lsb = 0x80,
458 .bw = 0,
459 .rxterm = 0,
461 .dfe_enable = 0,
462 .dfe_tap = 0,
463 .tx_tap_dly = 0,
464 .tx_tap_adv = 0,
468 .tx_pre_div = 0,
469 .fifo_ck_div = 0,
470 .pre_divsel = 0,
476 .com_tx_reserve_msb = (0x26 << 1),
477 .com_tx_reserve_lsb = (0xf << 4),
479 .tx_reserve_msb = 0x8,
480 .tx_reserve_lsb = 0x8a,
481 .bw = 0,
482 .cfg_pi_bw_3_0 = 0,
484 .dfe_enable = 0,
485 .dfe_tap = 0,
486 .tx_tap_dly = 0,
487 .tx_tap_adv = 0,
491 .tx_pre_div = 0,
493 .pre_divsel = 0,
499 .com_tx_reserve_msb = (0x26 << 1),
500 .com_tx_reserve_lsb = 0xf0,
501 .cfg_itx_ipcml_base = 0,
502 .tx_reserve_msb = 0x8,
503 .tx_reserve_lsb = 0xce,
504 .bw = 0,
505 .rxterm = 0,
506 .cfg_pi_bw_3_0 = 0,
507 .dfe_enable = 0,
508 .dfe_tap = 0,
509 .tx_tap_dly = 0,
510 .tx_tap_adv = 0,
516 .cfg_en_adv = 0,
518 .cfg_en_dly = 0,
519 .cfg_tap_adv_3_0 = 0,
521 .cfg_tap_dly_4_0 = 0,
523 .cfg_vga_cp_2_0 = 0,
524 .cfg_eq_res_3_0 = 0xa,
526 .cfg_eq_c_force_3_0 = 0x8,
527 .cfg_alos_thr_3_0 = 0x3,
533 .cfg_tap_adv_3_0 = 0,
535 .cfg_tap_dly_4_0 = 0xc,
536 .cfg_vga_ctrl_3_0 = 0xa,
537 .cfg_vga_cp_2_0 = 0x4,
538 .cfg_eq_res_3_0 = 0xa,
540 .cfg_eq_c_force_3_0 = 0xF,
541 .cfg_alos_thr_3_0 = 0x3,
550 .cfg_vga_ctrl_3_0 = 0xa,
552 .cfg_eq_res_3_0 = 0xa,
554 .cfg_eq_c_force_3_0 = 0xf,
555 .cfg_alos_thr_3_0 = 0x0,
563 .rate = 0x0,
565 .dfe_tap = 0x1f,
566 .pi_bw_gen1 = 0x0,
567 .duty_cycle = 0x2,
572 .rate = 0x1,
573 .dfe_enable = 0,
574 .dfe_tap = 0,
575 .pi_bw_gen1 = 0x5,
576 .duty_cycle = 0x0,
581 .rate = 0x1,
582 .dfe_enable = 0,
583 .dfe_tap = 0,
584 .pi_bw_gen1 = 0x5,
585 .duty_cycle = 0x0,
590 .rate = 0x1,
591 .dfe_enable = 0,
592 .dfe_tap = 0,
593 .pi_bw_gen1 = 0x5,
594 .duty_cycle = 0x0,
599 .rate = 0x2,
600 .dfe_enable = 0,
601 .dfe_tap = 0,
602 .pi_bw_gen1 = 0x7,
603 .duty_cycle = 0x0,
608 .rate = 0x3,
609 .dfe_enable = 0,
610 .dfe_tap = 0,
611 .pi_bw_gen1 = 0x7,
612 .duty_cycle = 0x0,
620 case 10: return 0; in sd25g28_get_iw_setting()
629 return 0; in sd25g28_get_iw_setting()
636 case 10: return 0; in sd10g28_get_iw_setting()
645 return 0; in sd10g28_get_iw_setting()
674 return 0; in sparx5_sd10g25_get_mode_preset()
711 return 0; in sparx5_sd10g28_get_mode_preset()
728 .cfg_vco_start_code_3_0 = 0, in sparx5_sd25g28_get_params()
734 .r_multi_lane_mode = 0, in sparx5_sd25g28_get_params()
737 .cfg_dfe_pd = mode->dfe_enable == 1 ? 0 : 1, in sparx5_sd25g28_get_params()
740 .cfg_dmux_pd = 0, in sparx5_sd25g28_get_params()
742 .cfg_erramp_pd = mode->dfe_enable == 1 ? 0 : 1, in sparx5_sd25g28_get_params()
745 .cfg_pd_ctle = 0, in sparx5_sd25g28_get_params()
747 .cfg_pmad_ck_pd = 0, in sparx5_sd25g28_get_params()
748 .cfg_pd_clk = 0, in sparx5_sd25g28_get_params()
749 .cfg_pd_cml = 0, in sparx5_sd25g28_get_params()
750 .cfg_pd_driver = 0, in sparx5_sd25g28_get_params()
753 .cfg_dcdr_pd = 0, in sparx5_sd25g28_get_params()
763 .cfg_iscan_en = 0, in sparx5_sd25g28_get_params()
764 .l1_pcs_en_fast_iscan = 0, in sparx5_sd25g28_get_params()
765 .l0_cfg_bw_1_0 = 0, in sparx5_sd25g28_get_params()
766 .cfg_en_dummy = 0, in sparx5_sd25g28_get_params()
775 .cfg_phase_man_4_0 = 0, in sparx5_sd25g28_get_params()
776 .cfg_quad_man_1_0 = 0, in sparx5_sd25g28_get_params()
779 .cfg_txcal_en = 0, in sparx5_sd25g28_get_params()
783 .cfg_pi_steps_1_0 = 0, in sparx5_sd25g28_get_params()
789 .cfg_rx_reserve_7_0 = 0xbf, in sparx5_sd25g28_get_params()
790 .cfg_rx_reserve_15_8 = 0x61, in sparx5_sd25g28_get_params()
792 .cfg_fom_selm = 0, in sparx5_sd25g28_get_params()
793 .cfg_rx_sp_ctle_1_0 = 0, in sparx5_sd25g28_get_params()
794 .cfg_isel_ctle_1_0 = 0, in sparx5_sd25g28_get_params()
807 .r_d_width_ctrl_from_hwt = 0, in sparx5_sd25g28_get_params()
813 .cfg_tx2rx_lp_en = 0, in sparx5_sd25g28_get_params()
814 .cfg_txlb_en = 0, in sparx5_sd25g28_get_params()
815 .cfg_rx2tx_lp_en = 0, in sparx5_sd25g28_get_params()
816 .cfg_rxlb_en = 0, in sparx5_sd25g28_get_params()
844 .r_pcs2pma_phymode_4_0 = 0, in sparx5_sd10g28_get_params()
845 .cfg_lane_id_2_0 = 0, in sparx5_sd10g28_get_params()
848 .cfg_dfe_pd = (mode->dfe_enable == 1) ? 0 : 1, in sparx5_sd10g28_get_params()
850 .cfg_erramp_pd = (mode->dfe_enable == 1) ? 0 : 1, in sparx5_sd10g28_get_params()
853 .cfg_pd_ctle = 0, in sparx5_sd10g28_get_params()
855 .cfg_pd_rx_cktree = 0, in sparx5_sd10g28_get_params()
856 .cfg_pd_clk = 0, in sparx5_sd10g28_get_params()
857 .cfg_pd_cml = 0, in sparx5_sd10g28_get_params()
858 .cfg_pd_driver = 0, in sparx5_sd10g28_get_params()
860 .cfg_d_cdr_pd = 0, in sparx5_sd10g28_get_params()
862 .cfg_rxdet_en = 0, in sparx5_sd10g28_get_params()
863 .cfg_rxdet_str = 0, in sparx5_sd10g28_get_params()
864 .r_multi_lane_mode = 0, in sparx5_sd10g28_get_params()
878 .cfg_en_preemph = 0, in sparx5_sd10g28_get_params()
879 .cfg_itx_ippreemp_base_1_0 = 0, in sparx5_sd10g28_get_params()
883 .cfg_dis_2nd_order = 0x1, in sparx5_sd10g28_get_params()
884 .cfg_rx_ssc_lh = 0x0, in sparx5_sd10g28_get_params()
885 .cfg_pi_floop_steps_1_0 = 0x0, in sparx5_sd10g28_get_params()
887 .cfg_pi_ext_dac_15_8 = (0 << 6), in sparx5_sd10g28_get_params()
899 .cfg_pi_steps = 0, in sparx5_sd10g28_get_params()
904 .cfg_itx_ipcml_base_1_0 = 0, in sparx5_sd10g28_get_params()
905 .cfg_ip_pre_base_1_0 = 0, in sparx5_sd10g28_get_params()
909 .r_en_auto_cdr_rstn = 0, in sparx5_sd10g28_get_params()
911 .cfg_pd_osdac_afe = 0, in sparx5_sd10g28_get_params()
912 .cfg_resetb_oscal_afe[0] = 0, in sparx5_sd10g28_get_params()
914 .cfg_center_spreading = 0, in sparx5_sd10g28_get_params()
919 .cfg_tx2rx_lp_en = 0, in sparx5_sd10g28_get_params()
920 .cfg_txlb_en = 0, in sparx5_sd10g28_get_params()
921 .cfg_rx2tx_lp_en = 0, in sparx5_sd10g28_get_params()
922 .cfg_rxlb_en = 0, in sparx5_sd10g28_get_params()
945 spd10g = 0; in sparx5_cmu_apply_cfg()
953 sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(0), in sparx5_cmu_apply_cfg()
963 sdx5_inst_rmw(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(0x1) | in sparx5_cmu_apply_cfg()
964 SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_SET(0x1) | in sparx5_cmu_apply_cfg()
965 SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_SET(0x1) | in sparx5_cmu_apply_cfg()
966 SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_SET(0x1) | in sparx5_cmu_apply_cfg()
967 SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(0x0), in sparx5_cmu_apply_cfg()
976 sdx5_inst_rmw(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(0), in sparx5_cmu_apply_cfg()
981 sdx5_inst_rmw(SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(0), in sparx5_cmu_apply_cfg()
986 sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_JC_BYP_SET(0x1), in sparx5_cmu_apply_cfg()
1016 sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(0), in sparx5_cmu_apply_cfg()
1023 sdx5_inst_rmw(SD_CMU_CMU_44_R_PLL_RSTN_SET(0), in sparx5_cmu_apply_cfg()
1039 dev_err(dev, "CMU PLL Loss of Lock: 0x%x\n", value); in sparx5_cmu_apply_cfg()
1042 sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_SET(0), in sparx5_cmu_apply_cfg()
1046 return 0; in sparx5_cmu_apply_cfg()
1056 spd10g = 0; in sparx5_cmu_cfg()
1073 [SPX5_SD10G28_CMU_AUX1] = { 0, 0, 3, 3, 3,
1104 for (i = 0; i < SPX5_CMU_MAX; i++) { in sparx5_serdes_cmu_power_off()
1108 sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(0), in sparx5_serdes_cmu_power_off()
1110 SD_CMU_CFG_SD_CMU_CFG(0)); in sparx5_serdes_cmu_power_off()
1112 sdx5_inst_rmw(SD_CMU_CMU_05_CFG_REFCK_TERM_EN_SET(0), in sparx5_serdes_cmu_power_off()
1114 SD_CMU_CMU_05(0)); in sparx5_serdes_cmu_power_off()
1116 sdx5_inst_rmw(SD_CMU_CMU_09_CFG_EN_TX_CK_DN_SET(0), in sparx5_serdes_cmu_power_off()
1118 SD_CMU_CMU_09(0)); in sparx5_serdes_cmu_power_off()
1122 SD_CMU_CMU_06(0)); in sparx5_serdes_cmu_power_off()
1124 sdx5_inst_rmw(SD_CMU_CMU_09_CFG_EN_TX_CK_UP_SET(0), in sparx5_serdes_cmu_power_off()
1126 SD_CMU_CMU_09(0)); in sparx5_serdes_cmu_power_off()
1130 SD_CMU_CMU_08(0)); in sparx5_serdes_cmu_power_off()
1138 SD_CMU_CMU_0D(0)); in sparx5_serdes_cmu_power_off()
1142 SD_CMU_CMU_06(0)); in sparx5_serdes_cmu_power_off()
1157 sdx5_rmw_addr(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(0), in sparx5_sd25g28_reset()
1177 sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xFF), in sparx5_sd25g28_apply_params()
1224 sdx5_rmw(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(0), in sparx5_sd25g28_apply_params()
1234 sdx5_rmw(SD25G_LANE_CMU_19_R_CK_RESETB_SET(0), in sparx5_sd25g28_apply_params()
1244 sdx5_rmw(SD25G_LANE_CMU_18_R_PLL_RSTN_SET(0), in sparx5_sd25g28_apply_params()
1287 sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0x00), in sparx5_sd25g28_apply_params()
1535 sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(0), in sparx5_sd25g28_apply_params()
1545 sdx5_rmw(SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(0), in sparx5_sd25g28_apply_params()
1550 sdx5_rmw(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(0), in sparx5_sd25g28_apply_params()
1564 sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xff), in sparx5_sd25g28_apply_params()
1573 dev_err(dev, "25G PLL Loss of Lock: 0x%x\n", value); in sparx5_sd25g28_apply_params()
1580 if (value != 0x1) { in sparx5_sd25g28_apply_params()
1581 dev_err(dev, "25G PMA Reset failed: 0x%x\n", value); in sparx5_sd25g28_apply_params()
1584 sdx5_rmw(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_SET(0x1), in sparx5_sd25g28_apply_params()
1589 sdx5_rmw(SD_LANE_25G_SD_SER_RST_SER_RST_SET(0x0), in sparx5_sd25g28_apply_params()
1594 sdx5_rmw(SD_LANE_25G_SD_DES_RST_DES_RST_SET(0x0), in sparx5_sd25g28_apply_params()
1599 sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0), in sparx5_sd25g28_apply_params()
1610 sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_SET(0), in sparx5_sd25g28_apply_params()
1615 sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_SET(0), in sparx5_sd25g28_apply_params()
1620 return 0; in sparx5_sd25g28_apply_params()
1632 sdx5_rmw_addr(SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(0), in sparx5_sd10g28_reset()
1651 return 0; in sparx5_sd10g28_apply_params()
1668 sdx5_inst_rmw(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_SET(0x0) | in sparx5_sd10g28_apply_params()
1669 SD10G_LANE_LANE_93_R_REG_MANUAL_SET(0x1) | in sparx5_sd10g28_apply_params()
1670 SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_SET(0x1) | in sparx5_sd10g28_apply_params()
1671 SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_SET(0x1) | in sparx5_sd10g28_apply_params()
1672 SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_SET(0x0), in sparx5_sd10g28_apply_params()
1681 sdx5_inst_rmw(SD10G_LANE_LANE_94_R_ISCAN_REG_SET(0x1) | in sparx5_sd10g28_apply_params()
1682 SD10G_LANE_LANE_94_R_TXEQ_REG_SET(0x1) | in sparx5_sd10g28_apply_params()
1683 SD10G_LANE_LANE_94_R_MISC_REG_SET(0x1) | in sparx5_sd10g28_apply_params()
1684 SD10G_LANE_LANE_94_R_SWING_REG_SET(0x1), in sparx5_sd10g28_apply_params()
1692 sdx5_inst_rmw(SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(0x1), in sparx5_sd10g28_apply_params()
1697 sdx5_inst_rmw(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_SET(0x0) | in sparx5_sd10g28_apply_params()
1698 SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_SET(0x0) | in sparx5_sd10g28_apply_params()
1699 SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_SET(0x1), in sparx5_sd10g28_apply_params()
1997 (params->cfg_resetb_oscal_afe[0]), in sparx5_sd10g28_apply_params()
2033 sdx5_rmw(SD_LANE_SD_LANE_CFG_MACRO_RST_SET(0), in sparx5_sd10g28_apply_params()
2068 dev_err(dev, "10G PMA Reset failed: 0x%x\n", value); in sparx5_sd10g28_apply_params()
2072 sdx5_rmw(SD_LANE_SD_SER_RST_SER_RST_SET(0x0), in sparx5_sd10g28_apply_params()
2077 sdx5_rmw(SD_LANE_SD_DES_RST_DES_RST_SET(0x0), in sparx5_sd10g28_apply_params()
2082 return 0; in sparx5_sd10g28_apply_params()
2091 .txinvert = 0, in sparx5_sd25g28_config()
2093 .com_pll_reserve = 0xf, in sparx5_sd25g28_config()
2114 .txinvert = 0, in sparx5_sd10g28_config()
2147 sdx5_inst_rmw(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(0), in sparx5_serdes_power_save()
2149 SD_LANE_25G_SD_LANE_CFG(0)); in sparx5_serdes_power_save()
2154 sd_lane_inst, SD_LANE_25G_QUIET_MODE_6G(0)); in sparx5_serdes_power_save()
2159 SD25G_LANE_LANE_04(0)); in sparx5_serdes_power_save()
2165 sdx5_inst_rmw(SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(0), in sparx5_serdes_power_save()
2167 SD_LANE_SD_LANE_CFG(0)); in sparx5_serdes_power_save()
2172 SD_LANE_QUIET_MODE_6G(0)); in sparx5_serdes_power_save()
2177 SD10G_LANE_LANE_06(0)); in sparx5_serdes_power_save()
2179 return 0; in sparx5_serdes_power_save()
2188 priv->coreclock == 500000000 ? 1 : 0; in sparx5_serdes_clock_config()
2195 return 0; in sparx5_serdes_clock_config()
2227 if (serdesmode < 0) { in sparx5_serdes_config()
2278 return 0; in sparx5_serdes_set_mode()
2293 return 0; in sparx5_serdes_set_media()
2309 return 0; in sparx5_serdes_set_speed()
2337 if (macro->speed == 0) in sparx5_serdes_validate()
2364 return 0; in sparx5_serdes_validate()
2410 return 0; in sparx5_phy_create()
2414 { TARGET_SD_CMU, 0x0 }, /* 0x610808000: sd_cmu_0 */
2415 { TARGET_SD_CMU + 1, 0x8000 }, /* 0x610810000: sd_cmu_1 */
2416 { TARGET_SD_CMU + 2, 0x10000 }, /* 0x610818000: sd_cmu_2 */
2417 { TARGET_SD_CMU + 3, 0x18000 }, /* 0x610820000: sd_cmu_3 */
2418 { TARGET_SD_CMU + 4, 0x20000 }, /* 0x610828000: sd_cmu_4 */
2419 { TARGET_SD_CMU + 5, 0x28000 }, /* 0x610830000: sd_cmu_5 */
2420 { TARGET_SD_CMU + 6, 0x30000 }, /* 0x610838000: sd_cmu_6 */
2421 { TARGET_SD_CMU + 7, 0x38000 }, /* 0x610840000: sd_cmu_7 */
2422 { TARGET_SD_CMU + 8, 0x40000 }, /* 0x610848000: sd_cmu_8 */
2423 { TARGET_SD_CMU_CFG, 0x48000 }, /* 0x610850000: sd_cmu_cfg_0 */
2424 { TARGET_SD_CMU_CFG + 1, 0x50000 }, /* 0x610858000: sd_cmu_cfg_1 */
2425 { TARGET_SD_CMU_CFG + 2, 0x58000 }, /* 0x610860000: sd_cmu_cfg_2 */
2426 { TARGET_SD_CMU_CFG + 3, 0x60000 }, /* 0x610868000: sd_cmu_cfg_3 */
2427 { TARGET_SD_CMU_CFG + 4, 0x68000 }, /* 0x610870000: sd_cmu_cfg_4 */
2428 { TARGET_SD_CMU_CFG + 5, 0x70000 }, /* 0x610878000: sd_cmu_cfg_5 */
2429 { TARGET_SD_CMU_CFG + 6, 0x78000 }, /* 0x610880000: sd_cmu_cfg_6 */
2430 { TARGET_SD_CMU_CFG + 7, 0x80000 }, /* 0x610888000: sd_cmu_cfg_7 */
2431 { TARGET_SD_CMU_CFG + 8, 0x88000 }, /* 0x610890000: sd_cmu_cfg_8 */
2432 { TARGET_SD6G_LANE, 0x90000 }, /* 0x610898000: sd6g_lane_0 */
2433 { TARGET_SD6G_LANE + 1, 0x98000 }, /* 0x6108a0000: sd6g_lane_1 */
2434 { TARGET_SD6G_LANE + 2, 0xa0000 }, /* 0x6108a8000: sd6g_lane_2 */
2435 { TARGET_SD6G_LANE + 3, 0xa8000 }, /* 0x6108b0000: sd6g_lane_3 */
2436 { TARGET_SD6G_LANE + 4, 0xb0000 }, /* 0x6108b8000: sd6g_lane_4 */
2437 { TARGET_SD6G_LANE + 5, 0xb8000 }, /* 0x6108c0000: sd6g_lane_5 */
2438 { TARGET_SD6G_LANE + 6, 0xc0000 }, /* 0x6108c8000: sd6g_lane_6 */
2439 { TARGET_SD6G_LANE + 7, 0xc8000 }, /* 0x6108d0000: sd6g_lane_7 */
2440 { TARGET_SD6G_LANE + 8, 0xd0000 }, /* 0x6108d8000: sd6g_lane_8 */
2441 { TARGET_SD6G_LANE + 9, 0xd8000 }, /* 0x6108e0000: sd6g_lane_9 */
2442 { TARGET_SD6G_LANE + 10, 0xe0000 }, /* 0x6108e8000: sd6g_lane_10 */
2443 { TARGET_SD6G_LANE + 11, 0xe8000 }, /* 0x6108f0000: sd6g_lane_11 */
2444 { TARGET_SD6G_LANE + 12, 0xf0000 }, /* 0x6108f8000: sd6g_lane_12 */
2445 { TARGET_SD10G_LANE, 0xf8000 }, /* 0x610900000: sd10g_lane_0 */
2446 { TARGET_SD10G_LANE + 1, 0x100000 }, /* 0x610908000: sd10g_lane_1 */
2447 { TARGET_SD10G_LANE + 2, 0x108000 }, /* 0x610910000: sd10g_lane_2 */
2448 { TARGET_SD10G_LANE + 3, 0x110000 }, /* 0x610918000: sd10g_lane_3 */
2449 { TARGET_SD_LANE, 0x1a0000 }, /* 0x6109a8000: sd_lane_0 */
2450 { TARGET_SD_LANE + 1, 0x1a8000 }, /* 0x6109b0000: sd_lane_1 */
2451 { TARGET_SD_LANE + 2, 0x1b0000 }, /* 0x6109b8000: sd_lane_2 */
2452 { TARGET_SD_LANE + 3, 0x1b8000 }, /* 0x6109c0000: sd_lane_3 */
2453 { TARGET_SD_LANE + 4, 0x1c0000 }, /* 0x6109c8000: sd_lane_4 */
2454 { TARGET_SD_LANE + 5, 0x1c8000 }, /* 0x6109d0000: sd_lane_5 */
2455 { TARGET_SD_LANE + 6, 0x1d0000 }, /* 0x6109d8000: sd_lane_6 */
2456 { TARGET_SD_LANE + 7, 0x1d8000 }, /* 0x6109e0000: sd_lane_7 */
2457 { TARGET_SD_LANE + 8, 0x1e0000 }, /* 0x6109e8000: sd_lane_8 */
2458 { TARGET_SD_LANE + 9, 0x1e8000 }, /* 0x6109f0000: sd_lane_9 */
2459 { TARGET_SD_LANE + 10, 0x1f0000 }, /* 0x6109f8000: sd_lane_10 */
2460 { TARGET_SD_LANE + 11, 0x1f8000 }, /* 0x610a00000: sd_lane_11 */
2461 { TARGET_SD_LANE + 12, 0x200000 }, /* 0x610a08000: sd_lane_12 */
2462 { TARGET_SD_LANE + 13, 0x208000 }, /* 0x610a10000: sd_lane_13 */
2463 { TARGET_SD_LANE + 14, 0x210000 }, /* 0x610a18000: sd_lane_14 */
2464 { TARGET_SD_LANE + 15, 0x218000 }, /* 0x610a20000: sd_lane_15 */
2465 { TARGET_SD_LANE + 16, 0x220000 }, /* 0x610a28000: sd_lane_16 */
2466 { TARGET_SD_CMU + 9, 0x400000 }, /* 0x610c08000: sd_cmu_9 */
2467 { TARGET_SD_CMU + 10, 0x408000 }, /* 0x610c10000: sd_cmu_10 */
2468 { TARGET_SD_CMU + 11, 0x410000 }, /* 0x610c18000: sd_cmu_11 */
2469 { TARGET_SD_CMU + 12, 0x418000 }, /* 0x610c20000: sd_cmu_12 */
2470 { TARGET_SD_CMU + 13, 0x420000 }, /* 0x610c28000: sd_cmu_13 */
2471 { TARGET_SD_CMU_CFG + 9, 0x428000 }, /* 0x610c30000: sd_cmu_cfg_9 */
2472 { TARGET_SD_CMU_CFG + 10, 0x430000 }, /* 0x610c38000: sd_cmu_cfg_10 */
2473 { TARGET_SD_CMU_CFG + 11, 0x438000 }, /* 0x610c40000: sd_cmu_cfg_11 */
2474 { TARGET_SD_CMU_CFG + 12, 0x440000 }, /* 0x610c48000: sd_cmu_cfg_12 */
2475 { TARGET_SD_CMU_CFG + 13, 0x448000 }, /* 0x610c50000: sd_cmu_cfg_13 */
2476 { TARGET_SD10G_LANE + 4, 0x450000 }, /* 0x610c58000: sd10g_lane_4 */
2477 { TARGET_SD10G_LANE + 5, 0x458000 }, /* 0x610c60000: sd10g_lane_5 */
2478 { TARGET_SD10G_LANE + 6, 0x460000 }, /* 0x610c68000: sd10g_lane_6 */
2479 { TARGET_SD10G_LANE + 7, 0x468000 }, /* 0x610c70000: sd10g_lane_7 */
2480 { TARGET_SD10G_LANE + 8, 0x470000 }, /* 0x610c78000: sd10g_lane_8 */
2481 { TARGET_SD10G_LANE + 9, 0x478000 }, /* 0x610c80000: sd10g_lane_9 */
2482 { TARGET_SD10G_LANE + 10, 0x480000 }, /* 0x610c88000: sd10g_lane_10 */
2483 { TARGET_SD10G_LANE + 11, 0x488000 }, /* 0x610c90000: sd10g_lane_11 */
2484 { TARGET_SD25G_LANE, 0x490000 }, /* 0x610c98000: sd25g_lane_0 */
2485 { TARGET_SD25G_LANE + 1, 0x498000 }, /* 0x610ca0000: sd25g_lane_1 */
2486 { TARGET_SD25G_LANE + 2, 0x4a0000 }, /* 0x610ca8000: sd25g_lane_2 */
2487 { TARGET_SD25G_LANE + 3, 0x4a8000 }, /* 0x610cb0000: sd25g_lane_3 */
2488 { TARGET_SD25G_LANE + 4, 0x4b0000 }, /* 0x610cb8000: sd25g_lane_4 */
2489 { TARGET_SD25G_LANE + 5, 0x4b8000 }, /* 0x610cc0000: sd25g_lane_5 */
2490 { TARGET_SD25G_LANE + 6, 0x4c0000 }, /* 0x610cc8000: sd25g_lane_6 */
2491 { TARGET_SD25G_LANE + 7, 0x4c8000 }, /* 0x610cd0000: sd25g_lane_7 */
2492 { TARGET_SD_LANE + 17, 0x550000 }, /* 0x610d58000: sd_lane_17 */
2493 { TARGET_SD_LANE + 18, 0x558000 }, /* 0x610d60000: sd_lane_18 */
2494 { TARGET_SD_LANE + 19, 0x560000 }, /* 0x610d68000: sd_lane_19 */
2495 { TARGET_SD_LANE + 20, 0x568000 }, /* 0x610d70000: sd_lane_20 */
2496 { TARGET_SD_LANE + 21, 0x570000 }, /* 0x610d78000: sd_lane_21 */
2497 { TARGET_SD_LANE + 22, 0x578000 }, /* 0x610d80000: sd_lane_22 */
2498 { TARGET_SD_LANE + 23, 0x580000 }, /* 0x610d88000: sd_lane_23 */
2499 { TARGET_SD_LANE + 24, 0x588000 }, /* 0x610d90000: sd_lane_24 */
2500 { TARGET_SD_LANE_25G, 0x590000 }, /* 0x610d98000: sd_lane_25g_25 */
2501 { TARGET_SD_LANE_25G + 1, 0x598000 }, /* 0x610da0000: sd_lane_25g_26 */
2502 { TARGET_SD_LANE_25G + 2, 0x5a0000 }, /* 0x610da8000: sd_lane_25g_27 */
2503 { TARGET_SD_LANE_25G + 3, 0x5a8000 }, /* 0x610db0000: sd_lane_25g_28 */
2504 { TARGET_SD_LANE_25G + 4, 0x5b0000 }, /* 0x610db8000: sd_lane_25g_29 */
2505 { TARGET_SD_LANE_25G + 5, 0x5b8000 }, /* 0x610dc0000: sd_lane_25g_30 */
2506 { TARGET_SD_LANE_25G + 6, 0x5c0000 }, /* 0x610dc8000: sd_lane_25g_31 */
2507 { TARGET_SD_LANE_25G + 7, 0x5c8000 }, /* 0x610dd0000: sd_lane_25g_32 */
2521 sidx = args->args[0]; in sparx5_serdes_xlate()
2524 for (idx = 0; idx < SPX5_SERDES_MAX; idx++) { in sparx5_serdes_xlate()
2565 if (clock == 0) { in sparx5_serdes_probe()
2571 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); in sparx5_serdes_probe()
2582 for (idx = 0; idx < ARRAY_SIZE(sparx5_serdes_iomap); idx++) { in sparx5_serdes_probe()
2587 for (idx = 0; idx < SPX5_SERDES_MAX; idx++) { in sparx5_serdes_probe()