1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
15 #include <linux/nvmem-consumer.h>
22 #include "phy-mtk-io.h"
24 /* version V1 sub-banks offset base address */
35 /* version V2/V3 sub-banks offset base address */
216 /* CDR Charge Pump P-path current adjustment */
235 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
244 /* I-path capacitance adjustment for Gen1 */
277 	/* avoid RX sensitivity level degradation only for mt8173 */
372 	[U3P_EFUSE_TX_IMP] = "tx-imp",
373 	[U3P_EFUSE_RX_IMP] = "rx-imp",
378 	struct mtk_phy_instance *inst = sf->private;  in u2_phy_params_show()
379 	const char *fname = file_dentry(sf->file)->d_iname;  in u2_phy_params_show()
380 	struct u2phy_banks *u2_banks = &inst->u2_banks;  in u2_phy_params_show()
381 	void __iomem *com = u2_banks->com;  in u2_phy_params_show()
405 		if (u2_banks->misc) {  in u2_phy_params_show()
406 			tmp = readl(u2_banks->misc + U3P_MISC_REG1);  in u2_phy_params_show()
443 	return single_open(file, u2_phy_params_show, inode->i_private);  in u2_phy_params_open()
449 	const char *fname = file_dentry(file)->d_iname;  in u2_phy_params_write()
450 	struct seq_file *sf = file->private_data;  in u2_phy_params_write()
451 	struct mtk_phy_instance *inst = sf->private;  in u2_phy_params_write()
452 	struct u2phy_banks *u2_banks = &inst->u2_banks;  in u2_phy_params_write()
453 	void __iomem *com = u2_banks->com;  in u2_phy_params_write()
476 		if (u2_banks->misc)  in u2_phy_params_write()
477 			mtk_phy_update_field(u2_banks->misc + U3P_MISC_REG1,  in u2_phy_params_write()
514 		debugfs_create_file(u2_phy_files[i], 0644, inst->phy->debugfs,  in u2_phy_dbgfs_files_create()
520 	struct mtk_phy_instance *inst = sf->private;  in u3_phy_params_show()
521 	const char *fname = file_dentry(sf->file)->d_iname;  in u3_phy_params_show()
522 	struct u3phy_banks *u3_banks = &inst->u3_banks;  in u3_phy_params_show()
534 		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);  in u3_phy_params_show()
540 		tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0);  in u3_phy_params_show()
546 		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0);  in u3_phy_params_show()
552 		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1);  in u3_phy_params_show()
569 	return single_open(file, u3_phy_params_show, inode->i_private);  in u3_phy_params_open()
575 	const char *fname = file_dentry(file)->d_iname;  in u3_phy_params_write()
576 	struct seq_file *sf = file->private_data;  in u3_phy_params_write()
577 	struct mtk_phy_instance *inst = sf->private;  in u3_phy_params_write()
578 	struct u3phy_banks *u3_banks = &inst->u3_banks;  in u3_phy_params_write()
579 	void __iomem *phyd = u3_banks->phyd;  in u3_phy_params_write()
599 		mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0,  in u3_phy_params_write()
634 		debugfs_create_file(u3_phy_files[i], 0644, inst->phy->debugfs,  in u3_phy_dbgfs_files_create()
640 	struct mtk_phy_instance *inst = sf->private;  in phy_type_show()
643 	switch (inst->type) {  in phy_type_show()
672 	debugfs_create_file("type", 0444, inst->phy->debugfs, inst, &phy_type_fops);  in phy_debugfs_init()
674 	switch (inst->type) {  in phy_debugfs_init()
697 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in hs_slew_rate_calibrate()
698 	void __iomem *fmreg = u2_banks->fmreg;  in hs_slew_rate_calibrate()
699 	void __iomem *com = u2_banks->com;  in hs_slew_rate_calibrate()
705 	if (tphy->pdata->version == MTK_PHY_V3)  in hs_slew_rate_calibrate()
709 	if (instance->eye_src)  in hs_slew_rate_calibrate()
723 	if (tphy->pdata->version == MTK_PHY_V1)  in hs_slew_rate_calibrate()
724 		tmp |= FIELD_PREP(P2F_RG_MONCLK_SEL, instance->index >> 1);  in hs_slew_rate_calibrate()
745 		tmp = tphy->src_ref_clk * tphy->src_coef;  in hs_slew_rate_calibrate()
752 	dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",  in hs_slew_rate_calibrate()
753 		instance->index, fm_out, calibration_val,  in hs_slew_rate_calibrate()
754 		tphy->src_ref_clk, tphy->src_coef);  in hs_slew_rate_calibrate()
767 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in u3_phy_instance_init()
768 	void __iomem *phya = u3_banks->phya;  in u3_phy_instance_init()
769 	void __iomem *phyd = u3_banks->phyd;  in u3_phy_instance_init()
772 	mtk_phy_set_bits(u3_banks->spllc + U3P_SPLLC_XTALCTL3,  in u3_phy_instance_init()
782 	mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_CDR1,  in u3_phy_instance_init()
793 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);  in u3_phy_instance_init()
799 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_pll_26m_set()
800 	void __iomem *com = u2_banks->com;  in u2_phy_pll_26m_set()
802 	if (!tphy->pdata->sw_pll_48m_to_26m)  in u2_phy_pll_26m_set()
818 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_init()
819 	void __iomem *com = u2_banks->com;  in u2_phy_instance_init()
820 	u32 index = instance->index;  in u2_phy_instance_init()
837 	if (tphy->pdata->avoid_rx_sen_degradation) {  in u2_phy_instance_init()
858 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);  in u2_phy_instance_init()
864 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_power_on()
865 	void __iomem *com = u2_banks->com;  in u2_phy_instance_power_on()
866 	u32 index = instance->index;  in u2_phy_instance_power_on()
875 	if (tphy->pdata->avoid_rx_sen_degradation && index) {  in u2_phy_instance_power_on()
880 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);  in u2_phy_instance_power_on()
886 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_power_off()
887 	void __iomem *com = u2_banks->com;  in u2_phy_instance_power_off()
888 	u32 index = instance->index;  in u2_phy_instance_power_off()
897 	if (tphy->pdata->avoid_rx_sen_degradation && index) {  in u2_phy_instance_power_off()
903 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);  in u2_phy_instance_power_off()
909 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_exit()
910 	void __iomem *com = u2_banks->com;  in u2_phy_instance_exit()
911 	u32 index = instance->index;  in u2_phy_instance_exit()
913 	if (tphy->pdata->avoid_rx_sen_degradation && index) {  in u2_phy_instance_exit()
924 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_set_mode()
927 	tmp = readl(u2_banks->com + U3P_U2PHYDTM1);  in u2_phy_instance_set_mode()
942 	writel(tmp, u2_banks->com + U3P_U2PHYDTM1);  in u2_phy_instance_set_mode()
948 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in pcie_phy_instance_init()
949 	void __iomem *phya = u3_banks->phya;  in pcie_phy_instance_init()
951 	if (tphy->pdata->version != MTK_PHY_V1)  in pcie_phy_instance_init()
964 	/* SSC delta -5000ppm */  in pcie_phy_instance_init()
983 	/* Tx Detect Rx Timing: 10us -> 5us */  in pcie_phy_instance_init()
984 	mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET1,  in pcie_phy_instance_init()
987 	mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET2,  in pcie_phy_instance_init()
992 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);  in pcie_phy_instance_init()
998 	struct u3phy_banks *bank = &instance->u3_banks;  in pcie_phy_instance_power_on()
1000 	mtk_phy_clear_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLD,  in pcie_phy_instance_power_on()
1003 	mtk_phy_clear_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLE,  in pcie_phy_instance_power_on()
1011 	struct u3phy_banks *bank = &instance->u3_banks;  in pcie_phy_instance_power_off()
1013 	mtk_phy_set_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLD,  in pcie_phy_instance_power_off()
1016 	mtk_phy_set_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLE,  in pcie_phy_instance_power_off()
1023 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in sata_phy_instance_init()
1024 	void __iomem *phyd = u3_banks->phyd;  in sata_phy_instance_init()
1062 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);  in sata_phy_instance_init()
1068 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in phy_v1_banks_init()
1069 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in phy_v1_banks_init()
1071 	switch (instance->type) {  in phy_v1_banks_init()
1073 		u2_banks->misc = NULL;  in phy_v1_banks_init()
1074 		u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;  in phy_v1_banks_init()
1075 		u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;  in phy_v1_banks_init()
1079 		u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;  in phy_v1_banks_init()
1080 		u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;  in phy_v1_banks_init()
1081 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;  in phy_v1_banks_init()
1082 		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;  in phy_v1_banks_init()
1085 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;  in phy_v1_banks_init()
1088 		dev_err(tphy->dev, "incompatible PHY type\n");  in phy_v1_banks_init()
1096 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in phy_v2_banks_init()
1097 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in phy_v2_banks_init()
1099 	switch (instance->type) {  in phy_v2_banks_init()
1101 		u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;  in phy_v2_banks_init()
1102 		u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;  in phy_v2_banks_init()
1103 		u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;  in phy_v2_banks_init()
1107 		u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;  in phy_v2_banks_init()
1108 		u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;  in phy_v2_banks_init()
1109 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;  in phy_v2_banks_init()
1110 		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;  in phy_v2_banks_init()
1113 		dev_err(tphy->dev, "incompatible PHY type\n");  in phy_v2_banks_init()
1121 	struct device *dev = &instance->phy->dev;  in phy_parse_property()
1123 	if (instance->type != PHY_TYPE_USB2)  in phy_parse_property()
1126 	instance->bc12_en = device_property_read_bool(dev, "mediatek,bc12");  in phy_parse_property()
1127 	device_property_read_u32(dev, "mediatek,eye-src",  in phy_parse_property()
1128 				 &instance->eye_src);  in phy_parse_property()
1129 	device_property_read_u32(dev, "mediatek,eye-vrt",  in phy_parse_property()
1130 				 &instance->eye_vrt);  in phy_parse_property()
1131 	device_property_read_u32(dev, "mediatek,eye-term",  in phy_parse_property()
1132 				 &instance->eye_term);  in phy_parse_property()
1134 				 &instance->intr);  in phy_parse_property()
1136 				 &instance->discth);  in phy_parse_property()
1137 	device_property_read_u32(dev, "mediatek,pre-emphasis",  in phy_parse_property()
1138 				 &instance->pre_emphasis);  in phy_parse_property()
1140 		instance->bc12_en, instance->eye_src,  in phy_parse_property()
1141 		instance->eye_vrt, instance->eye_term,  in phy_parse_property()
1142 		instance->intr, instance->discth);  in phy_parse_property()
1143 	dev_dbg(dev, "pre-emp:%d\n", instance->pre_emphasis);  in phy_parse_property()
1149 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_props_set()
1150 	void __iomem *com = u2_banks->com;  in u2_phy_props_set()
1152 	if (instance->bc12_en) /* BC1.2 path Enable */  in u2_phy_props_set()
1155 	if (tphy->pdata->version < MTK_PHY_V3 && instance->eye_src)  in u2_phy_props_set()
1157 				     instance->eye_src);  in u2_phy_props_set()
1159 	if (instance->eye_vrt)  in u2_phy_props_set()
1161 				     instance->eye_vrt);  in u2_phy_props_set()
1163 	if (instance->eye_term)  in u2_phy_props_set()
1165 				     instance->eye_term);  in u2_phy_props_set()
1167 	if (instance->intr) {  in u2_phy_props_set()
1168 		if (u2_banks->misc)  in u2_phy_props_set()
1169 			mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1,  in u2_phy_props_set()
1173 				     instance->intr);  in u2_phy_props_set()
1176 	if (instance->discth)  in u2_phy_props_set()
1178 				     instance->discth);  in u2_phy_props_set()
1180 	if (instance->pre_emphasis)  in u2_phy_props_set()
1182 				     instance->pre_emphasis);  in u2_phy_props_set()
1193 	if (!of_property_read_bool(dn, "mediatek,syscon-type"))  in phy_type_syscon_get()
1196 	ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type",  in phy_type_syscon_get()
1201 	instance->type_sw_reg = args.args[0];  in phy_type_syscon_get()
1202 	instance->type_sw_index = args.args[1] & 0x3; /* <=3 */  in phy_type_syscon_get()
1203 	instance->type_sw = syscon_node_to_regmap(args.np);  in phy_type_syscon_get()
1205 	dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n",  in phy_type_syscon_get()
1206 		 instance->type_sw_reg, instance->type_sw_index);  in phy_type_syscon_get()
1208 	return PTR_ERR_OR_ZERO(instance->type_sw);  in phy_type_syscon_get()
1216 	if (!instance->type_sw)  in phy_type_set()
1219 	switch (instance->type) {  in phy_type_set()
1237 	offset = instance->type_sw_index * BITS_PER_BYTE;  in phy_type_set()
1238 	regmap_update_bits(instance->type_sw, instance->type_sw_reg,  in phy_type_set()
1246 	struct device *dev = &instance->phy->dev;  in phy_efuse_get()
1250 	if (!tphy->pdata->sw_efuse_supported) {  in phy_efuse_get()
1251 		instance->efuse_sw_en = 0;  in phy_efuse_get()
1256 	instance->efuse_sw_en = device_property_read_bool(dev, "nvmem-cells");  in phy_efuse_get()
1257 	if (!instance->efuse_sw_en)  in phy_efuse_get()
1260 	switch (instance->type) {  in phy_efuse_get()
1262 		ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);  in phy_efuse_get()
1269 		if (!instance->efuse_intr) {  in phy_efuse_get()
1271 			instance->efuse_sw_en = 0;  in phy_efuse_get()
1275 		dev_dbg(dev, "u2 efuse - intr %x\n", instance->efuse_intr);  in phy_efuse_get()
1280 		ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);  in phy_efuse_get()
1286 		ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp", &instance->efuse_rx_imp);  in phy_efuse_get()
1292 		ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp", &instance->efuse_tx_imp);  in phy_efuse_get()
1299 		if (!instance->efuse_intr &&  in phy_efuse_get()
1300 		    !instance->efuse_rx_imp &&  in phy_efuse_get()
1301 		    !instance->efuse_tx_imp) {  in phy_efuse_get()
1303 			instance->efuse_sw_en = 0;  in phy_efuse_get()
1307 		dev_dbg(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n",  in phy_efuse_get()
1308 			instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp);  in phy_efuse_get()
1311 		dev_err(dev, "no sw efuse for type %d\n", instance->type);  in phy_efuse_get()
1312 		ret = -EINVAL;  in phy_efuse_get()
1320 	struct device *dev = &instance->phy->dev;  in phy_efuse_set()
1321 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in phy_efuse_set()
1322 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in phy_efuse_set()
1324 	if (!instance->efuse_sw_en)  in phy_efuse_set()
1327 	switch (instance->type) {  in phy_efuse_set()
1329 		mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1, MR1_EFUSE_AUTO_LOAD_DIS);  in phy_efuse_set()
1331 		mtk_phy_update_field(u2_banks->com + U3P_USBPHYACR1, PA1_RG_INTR_CAL,  in phy_efuse_set()
1332 				     instance->efuse_intr);  in phy_efuse_set()
1336 		mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_RSV, P3D_RG_EFUSE_AUTO_LOAD_DIS);  in phy_efuse_set()
1338 		mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL,  in phy_efuse_set()
1339 				    instance->efuse_tx_imp);  in phy_efuse_set()
1340 		mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_FORCE_TX_IMPEL);  in phy_efuse_set()
1342 		mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL,  in phy_efuse_set()
1343 				    instance->efuse_rx_imp);  in phy_efuse_set()
1344 		mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_FORCE_RX_IMPEL);  in phy_efuse_set()
1346 		mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_IEXT_INTR,  in phy_efuse_set()
1347 				    instance->efuse_intr);  in phy_efuse_set()
1350 		dev_warn(dev, "no sw efuse for type %d\n", instance->type);  in phy_efuse_set()
1358 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_init()
1361 	ret = clk_bulk_prepare_enable(TPHY_CLKS_CNT, instance->clks);  in mtk_phy_init()
1367 	switch (instance->type) {  in mtk_phy_init()
1385 		dev_err(tphy->dev, "incompatible PHY type\n");  in mtk_phy_init()
1386 		clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks);  in mtk_phy_init()
1387 		return -EINVAL;  in mtk_phy_init()
1396 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_power_on()
1398 	if (instance->type == PHY_TYPE_USB2) {  in mtk_phy_power_on()
1401 	} else if (instance->type == PHY_TYPE_PCIE) {  in mtk_phy_power_on()
1411 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_power_off()
1413 	if (instance->type == PHY_TYPE_USB2)  in mtk_phy_power_off()
1415 	else if (instance->type == PHY_TYPE_PCIE)  in mtk_phy_power_off()
1424 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_exit()
1426 	if (instance->type == PHY_TYPE_USB2)  in mtk_phy_exit()
1429 	clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks);  in mtk_phy_exit()
1436 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_set_mode()
1438 	if (instance->type == PHY_TYPE_USB2)  in mtk_phy_set_mode()
1449 	struct device_node *phy_np = args->np;  in mtk_phy_xlate()
1453 	if (args->args_count != 1) {  in mtk_phy_xlate()
1455 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
1458 	for (index = 0; index < tphy->nphys; index++)  in mtk_phy_xlate()
1459 		if (phy_np == tphy->phys[index]->phy->dev.of_node) {  in mtk_phy_xlate()
1460 			instance = tphy->phys[index];  in mtk_phy_xlate()
1466 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
1469 	instance->type = args->args[0];  in mtk_phy_xlate()
1470 	if (!(instance->type == PHY_TYPE_USB2 ||  in mtk_phy_xlate()
1471 	      instance->type == PHY_TYPE_USB3 ||  in mtk_phy_xlate()
1472 	      instance->type == PHY_TYPE_PCIE ||  in mtk_phy_xlate()
1473 	      instance->type == PHY_TYPE_SATA ||  in mtk_phy_xlate()
1474 	      instance->type == PHY_TYPE_SGMII)) {  in mtk_phy_xlate()
1475 		dev_err(dev, "unsupported device type: %d\n", instance->type);  in mtk_phy_xlate()
1476 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
1479 	switch (tphy->pdata->version) {  in mtk_phy_xlate()
1489 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
1500 	return instance->phy;  in mtk_phy_xlate()
1540 	{ .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata },
1541 	{ .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata },
1542 	{ .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
1543 	{ .compatible = "mediatek,mt8195-tphy", .data = &mt8195_pdata },
1544 	{ .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
1545 	{ .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
1546 	{ .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata },
1553 	struct device *dev = &pdev->dev;  in mtk_tphy_probe()
1554 	struct device_node *np = dev->of_node;  in mtk_tphy_probe()
1564 		return -ENOMEM;  in mtk_tphy_probe()
1566 	tphy->pdata = of_device_get_match_data(dev);  in mtk_tphy_probe()
1567 	if (!tphy->pdata)  in mtk_tphy_probe()
1568 		return -EINVAL;  in mtk_tphy_probe()
1570 	tphy->nphys = of_get_child_count(np);  in mtk_tphy_probe()
1571 	tphy->phys = devm_kcalloc(dev, tphy->nphys,  in mtk_tphy_probe()
1572 				       sizeof(*tphy->phys), GFP_KERNEL);  in mtk_tphy_probe()
1573 	if (!tphy->phys)  in mtk_tphy_probe()
1574 		return -ENOMEM;  in mtk_tphy_probe()
1576 	tphy->dev = dev;  in mtk_tphy_probe()
1581 	if (sif_res && tphy->pdata->version == MTK_PHY_V1) {  in mtk_tphy_probe()
1583 		tphy->sif_base = devm_ioremap_resource(dev, sif_res);  in mtk_tphy_probe()
1584 		if (IS_ERR(tphy->sif_base)) {  in mtk_tphy_probe()
1586 			return PTR_ERR(tphy->sif_base);  in mtk_tphy_probe()
1590 	if (tphy->pdata->version < MTK_PHY_V3) {  in mtk_tphy_probe()
1591 		tphy->src_ref_clk = U3P_REF_CLK;  in mtk_tphy_probe()
1592 		tphy->src_coef = U3P_SLEW_RATE_COEF;  in mtk_tphy_probe()
1594 		device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",  in mtk_tphy_probe()
1595 					 &tphy->src_ref_clk);  in mtk_tphy_probe()
1596 		device_property_read_u32(dev, "mediatek,src-coef",  in mtk_tphy_probe()
1597 					 &tphy->src_coef);  in mtk_tphy_probe()
1609 			retval = -ENOMEM;  in mtk_tphy_probe()
1613 		tphy->phys[port] = instance;  in mtk_tphy_probe()
1622 		subdev = &phy->dev;  in mtk_tphy_probe()
1625 			dev_err(subdev, "failed to get address resource(id-%d)\n",  in mtk_tphy_probe()
1630 		instance->port_base = devm_ioremap_resource(subdev, &res);  in mtk_tphy_probe()
1631 		if (IS_ERR(instance->port_base)) {  in mtk_tphy_probe()
1632 			retval = PTR_ERR(instance->port_base);  in mtk_tphy_probe()
1636 		instance->phy = phy;  in mtk_tphy_probe()
1637 		instance->index = port;  in mtk_tphy_probe()
1641 		clks = instance->clks;  in mtk_tphy_probe()
1664 		.name	= "mtk-tphy",
1672 MODULE_DESCRIPTION("MediaTek T-PHY driver");