7  * This implementation is based on old RISC-V perf and ARM perf event code
21 static bool riscv_perf_user_access(struct perf_event *event)  in riscv_perf_user_access()  argument
23 	return ((event->attr.type == PERF_TYPE_HARDWARE) ||  in riscv_perf_user_access()
24 		(event->attr.type == PERF_TYPE_HW_CACHE) ||  in riscv_perf_user_access()
25 		(event->attr.type == PERF_TYPE_RAW)) &&  in riscv_perf_user_access()
26 		!!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT) &&  in riscv_perf_user_access()
27 		(event->hw.idx != -1);  in riscv_perf_user_access()
30 void arch_perf_update_userpage(struct perf_event *event,  in arch_perf_update_userpage()  argument
40 	userpg->cap_user_rdpmc = riscv_perf_user_access(event);  in arch_perf_update_userpage()
49 		userpg->pmc_width = to_riscv_pmu(event->pmu)->ctr_get_width(event->hw.idx) + 1;  in arch_perf_update_userpage()
147 u64 riscv_pmu_ctr_get_width_mask(struct perf_event *event)  in riscv_pmu_ctr_get_width_mask()  argument
150 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_ctr_get_width_mask()
151 	struct hw_perf_event *hwc = &event->hw;  in riscv_pmu_ctr_get_width_mask()
170 u64 riscv_pmu_event_update(struct perf_event *event)  in riscv_pmu_event_update()  argument
172 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_event_update()
173 	struct hw_perf_event *hwc = &event->hw;  in riscv_pmu_event_update()
181 	cmask = riscv_pmu_ctr_get_width_mask(event);  in riscv_pmu_event_update()
185 		new_raw_count = rvpmu->ctr_read(event);  in riscv_pmu_event_update()
191 	local64_add(delta, &event->count);  in riscv_pmu_event_update()
197 void riscv_pmu_stop(struct perf_event *event, int flags)  in riscv_pmu_stop()  argument
199 	struct hw_perf_event *hwc = &event->hw;  in riscv_pmu_stop()
200 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_stop()
206 			rvpmu->ctr_stop(event, 0);  in riscv_pmu_stop()
209 		riscv_pmu_event_update(event);  in riscv_pmu_stop()
214 int riscv_pmu_event_set_period(struct perf_event *event)  in riscv_pmu_event_set_period()  argument
216 	struct hw_perf_event *hwc = &event->hw;  in riscv_pmu_event_set_period()
220 	uint64_t max_period = riscv_pmu_ctr_get_width_mask(event);  in riscv_pmu_event_set_period()
247 	perf_event_update_userpage(event);  in riscv_pmu_event_set_period()
252 void riscv_pmu_start(struct perf_event *event, int flags)  in riscv_pmu_start()  argument
254 	struct hw_perf_event *hwc = &event->hw;  in riscv_pmu_start()
255 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_start()
256 	uint64_t max_period = riscv_pmu_ctr_get_width_mask(event);  in riscv_pmu_start()
260 		WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));  in riscv_pmu_start()
263 	riscv_pmu_event_set_period(event);  in riscv_pmu_start()
265 	rvpmu->ctr_start(event, init_val);  in riscv_pmu_start()
266 	perf_event_update_userpage(event);  in riscv_pmu_start()
269 static int riscv_pmu_add(struct perf_event *event, int flags)  in riscv_pmu_add()  argument
271 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_add()
273 	struct hw_perf_event *hwc = &event->hw;  in riscv_pmu_add()
276 	idx = rvpmu->ctr_get_idx(event);  in riscv_pmu_add()
281 	cpuc->events[idx] = event;  in riscv_pmu_add()
285 		riscv_pmu_start(event, PERF_EF_RELOAD);  in riscv_pmu_add()
288 	perf_event_update_userpage(event);  in riscv_pmu_add()
293 static void riscv_pmu_del(struct perf_event *event, int flags)  in riscv_pmu_del()  argument
295 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_del()
297 	struct hw_perf_event *hwc = &event->hw;  in riscv_pmu_del()
299 	riscv_pmu_stop(event, PERF_EF_UPDATE);  in riscv_pmu_del()
303 		rvpmu->ctr_stop(event, RISCV_PMU_STOP_FLAG_RESET);  in riscv_pmu_del()
306 		rvpmu->ctr_clear_idx(event);  in riscv_pmu_del()
307 	perf_event_update_userpage(event);  in riscv_pmu_del()
311 static void riscv_pmu_read(struct perf_event *event)  in riscv_pmu_read()  argument
313 	riscv_pmu_event_update(event);  in riscv_pmu_read()
316 static int riscv_pmu_event_init(struct perf_event *event)  in riscv_pmu_event_init()  argument
318 	struct hw_perf_event *hwc = &event->hw;  in riscv_pmu_event_init()
319 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_event_init()
325 	mapped_event = rvpmu->event_map(event, &event_config);  in riscv_pmu_event_init()
327 		pr_debug("event %x:%llx not supported\n", event->attr.type,  in riscv_pmu_event_init()
328 			 event->attr.config);  in riscv_pmu_event_init()
333 	 * idx is set to -1 because the index of a general event should not be  in riscv_pmu_event_init()
343 		rvpmu->event_init(event);  in riscv_pmu_event_init()
345 	if (!is_sampling_event(event)) {  in riscv_pmu_event_init()
352 		cmask = riscv_pmu_ctr_get_width_mask(event);  in riscv_pmu_event_init()
361 static int riscv_pmu_event_idx(struct perf_event *event)  in riscv_pmu_event_idx()  argument
363 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_event_idx()
365 	if (!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT))  in riscv_pmu_event_idx()
369 		return rvpmu->csr_index(event) + 1;  in riscv_pmu_event_idx()
374 static void riscv_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm)  in riscv_pmu_event_mapped()  argument
376 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_event_mapped()
379 		rvpmu->event_mapped(event, mm);  in riscv_pmu_event_mapped()
380 		perf_event_update_userpage(event);  in riscv_pmu_event_mapped()
384 static void riscv_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm)  in riscv_pmu_event_unmapped()  argument
386 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);  in riscv_pmu_event_unmapped()
389 		rvpmu->event_unmapped(event, mm);  in riscv_pmu_event_unmapped()
390 		perf_event_update_userpage(event);  in riscv_pmu_event_unmapped()