Lines Matching +full:ddr +full:- +full:pmu
1 // SPDX-License-Identifier: GPL-2.0
43 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
50 /* DDR Perf hardware feature */
55 unsigned int quirks; /* quirks needed for different DDR Perf core */
56 const char *identifier; /* system PMU identifier for userspace */
86 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
87 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
88 { .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data},
89 { .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data},
90 { .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data},
91 { .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data},
97 struct pmu pmu; member
114 struct ddr_pmu *pmu = dev_get_drvdata(dev); in ddr_perf_identifier_show() local
116 return sysfs_emit(page, "%s\n", pmu->devtype_data->identifier); in ddr_perf_identifier_show()
124 struct ddr_pmu *pmu = dev_get_drvdata(dev); in ddr_perf_identifier_attr_visible() local
126 if (!pmu->devtype_data->identifier) in ddr_perf_identifier_attr_visible()
128 return attr->mode; in ddr_perf_identifier_attr_visible()
150 static u32 ddr_perf_filter_cap_get(struct ddr_pmu *pmu, int cap) in ddr_perf_filter_cap_get() argument
152 u32 quirks = pmu->devtype_data->quirks; in ddr_perf_filter_cap_get()
171 struct ddr_pmu *pmu = dev_get_drvdata(dev); in ddr_perf_filter_cap_show() local
174 int cap = (long)ea->var; in ddr_perf_filter_cap_show()
176 return sysfs_emit(buf, "%u\n", ddr_perf_filter_cap_get(pmu, cap)); in ddr_perf_filter_cap_show()
201 struct ddr_pmu *pmu = dev_get_drvdata(dev); in ddr_perf_cpumask_show() local
203 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu)); in ddr_perf_cpumask_show()
225 return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id); in ddr_pmu_event_show()
234 IMX8_DDR_PMU_EVENT_ATTR(read-accesses, 0x04),
235 IMX8_DDR_PMU_EVENT_ATTR(write-accesses, 0x05),
236 IMX8_DDR_PMU_EVENT_ATTR(read-queue-depth, 0x08),
237 IMX8_DDR_PMU_EVENT_ATTR(write-queue-depth, 0x09),
238 IMX8_DDR_PMU_EVENT_ATTR(lp-read-credit-cnt, 0x10),
239 IMX8_DDR_PMU_EVENT_ATTR(hp-read-credit-cnt, 0x11),
240 IMX8_DDR_PMU_EVENT_ATTR(write-credit-cnt, 0x12),
241 IMX8_DDR_PMU_EVENT_ATTR(read-command, 0x20),
242 IMX8_DDR_PMU_EVENT_ATTR(write-command, 0x21),
243 IMX8_DDR_PMU_EVENT_ATTR(read-modify-write-command, 0x22),
244 IMX8_DDR_PMU_EVENT_ATTR(hp-read, 0x23),
245 IMX8_DDR_PMU_EVENT_ATTR(hp-req-nocredit, 0x24),
246 IMX8_DDR_PMU_EVENT_ATTR(hp-xact-credit, 0x25),
247 IMX8_DDR_PMU_EVENT_ATTR(lp-req-nocredit, 0x26),
248 IMX8_DDR_PMU_EVENT_ATTR(lp-xact-credit, 0x27),
249 IMX8_DDR_PMU_EVENT_ATTR(wr-xact-credit, 0x29),
250 IMX8_DDR_PMU_EVENT_ATTR(read-cycles, 0x2a),
251 IMX8_DDR_PMU_EVENT_ATTR(write-cycles, 0x2b),
252 IMX8_DDR_PMU_EVENT_ATTR(read-write-transition, 0x30),
255 IMX8_DDR_PMU_EVENT_ATTR(load-mode, 0x33),
256 IMX8_DDR_PMU_EVENT_ATTR(perf-mwr, 0x34),
258 IMX8_DDR_PMU_EVENT_ATTR(read-activate, 0x36),
261 IMX8_DDR_PMU_EVENT_ATTR(raw-hazard, 0x39),
262 IMX8_DDR_PMU_EVENT_ATTR(axid-read, 0x41),
263 IMX8_DDR_PMU_EVENT_ATTR(axid-write, 0x42),
272 PMU_FORMAT_ATTR(event, "config:0-7");
273 PMU_FORMAT_ATTR(axi_id, "config1:0-15");
274 PMU_FORMAT_ATTR(axi_mask, "config1:16-31");
299 return event->attr.config == 0x41 || event->attr.config == 0x42; in ddr_perf_is_filtered()
304 return event->attr.config1; in ddr_perf_filter_val()
320 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_is_enhanced_filtered() local
322 filt = pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED; in ddr_perf_is_enhanced_filtered()
327 static u32 ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event) in ddr_perf_alloc_counter() argument
337 if (pmu->events[EVENT_CYCLES_COUNTER] == NULL) in ddr_perf_alloc_counter()
340 return -ENOENT; in ddr_perf_alloc_counter()
344 if (pmu->events[i] == NULL) in ddr_perf_alloc_counter()
348 return -ENOENT; in ddr_perf_alloc_counter()
351 static void ddr_perf_free_counter(struct ddr_pmu *pmu, int counter) in ddr_perf_free_counter() argument
353 pmu->events[counter] = NULL; in ddr_perf_free_counter()
356 static u32 ddr_perf_read_counter(struct ddr_pmu *pmu, int counter) in ddr_perf_read_counter() argument
358 struct perf_event *event = pmu->events[counter]; in ddr_perf_read_counter()
359 void __iomem *base = pmu->base; in ddr_perf_read_counter()
362 * return bytes instead of bursts from ddr transaction for in ddr_perf_read_counter()
363 * axid-read and axid-write event if PMU core supports enhanced in ddr_perf_read_counter()
373 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_event_init() local
374 struct hw_perf_event *hwc = &event->hw; in ddr_perf_event_init()
377 if (event->attr.type != event->pmu->type) in ddr_perf_event_init()
378 return -ENOENT; in ddr_perf_event_init()
380 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) in ddr_perf_event_init()
381 return -EOPNOTSUPP; in ddr_perf_event_init()
383 if (event->cpu < 0) { in ddr_perf_event_init()
384 dev_warn(pmu->dev, "Can't provide per-task data!\n"); in ddr_perf_event_init()
385 return -EOPNOTSUPP; in ddr_perf_event_init()
391 * periodically read when a hrtimer aka cpu-clock leader triggers). in ddr_perf_event_init()
393 if (event->group_leader->pmu != event->pmu && in ddr_perf_event_init()
394 !is_software_event(event->group_leader)) in ddr_perf_event_init()
395 return -EINVAL; in ddr_perf_event_init()
397 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) { in ddr_perf_event_init()
398 if (!ddr_perf_filters_compatible(event, event->group_leader)) in ddr_perf_event_init()
399 return -EINVAL; in ddr_perf_event_init()
400 for_each_sibling_event(sibling, event->group_leader) { in ddr_perf_event_init()
402 return -EINVAL; in ddr_perf_event_init()
406 for_each_sibling_event(sibling, event->group_leader) { in ddr_perf_event_init()
407 if (sibling->pmu != event->pmu && in ddr_perf_event_init()
409 return -EINVAL; in ddr_perf_event_init()
412 event->cpu = pmu->cpu; in ddr_perf_event_init()
413 hwc->idx = -1; in ddr_perf_event_init()
418 static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, in ddr_perf_counter_enable() argument
431 writel(0, pmu->base + reg); in ddr_perf_counter_enable()
440 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) { in ddr_perf_counter_enable()
445 writel(val, pmu->base + reg); in ddr_perf_counter_enable()
448 val = readl_relaxed(pmu->base + reg) & CNTL_EN_MASK; in ddr_perf_counter_enable()
449 writel(val, pmu->base + reg); in ddr_perf_counter_enable()
453 static bool ddr_perf_counter_overflow(struct ddr_pmu *pmu, int counter) in ddr_perf_counter_overflow() argument
457 val = readl_relaxed(pmu->base + counter * 4 + COUNTER_CNTL); in ddr_perf_counter_overflow()
462 static void ddr_perf_counter_clear(struct ddr_pmu *pmu, int counter) in ddr_perf_counter_clear() argument
467 val = readl_relaxed(pmu->base + reg); in ddr_perf_counter_clear()
469 writel(val, pmu->base + reg); in ddr_perf_counter_clear()
472 writel(val, pmu->base + reg); in ddr_perf_counter_clear()
477 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_event_update() local
478 struct hw_perf_event *hwc = &event->hw; in ddr_perf_event_update()
480 int counter = hwc->idx; in ddr_perf_event_update()
483 new_raw_count = ddr_perf_read_counter(pmu, counter); in ddr_perf_event_update()
485 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) { in ddr_perf_event_update()
490 local64_add(new_raw_count, &event->count); in ddr_perf_event_update()
499 ret = ddr_perf_counter_overflow(pmu, counter); in ddr_perf_event_update()
501 dev_warn_ratelimited(pmu->dev, "events lost due to counter overflow (config 0x%llx)\n", in ddr_perf_event_update()
502 event->attr.config); in ddr_perf_event_update()
506 ddr_perf_counter_clear(pmu, counter); in ddr_perf_event_update()
511 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_event_start() local
512 struct hw_perf_event *hwc = &event->hw; in ddr_perf_event_start()
513 int counter = hwc->idx; in ddr_perf_event_start()
515 local64_set(&hwc->prev_count, 0); in ddr_perf_event_start()
517 ddr_perf_counter_enable(pmu, event->attr.config, counter, true); in ddr_perf_event_start()
519 if (!pmu->active_counter++) in ddr_perf_event_start()
520 ddr_perf_counter_enable(pmu, EVENT_CYCLES_ID, in ddr_perf_event_start()
523 hwc->state = 0; in ddr_perf_event_start()
528 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_event_add() local
529 struct hw_perf_event *hwc = &event->hw; in ddr_perf_event_add()
531 int cfg = event->attr.config; in ddr_perf_event_add()
532 int cfg1 = event->attr.config1; in ddr_perf_event_add()
534 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) { in ddr_perf_event_add()
538 if (pmu->events[i] && in ddr_perf_event_add()
539 !ddr_perf_filters_compatible(event, pmu->events[i])) in ddr_perf_event_add()
540 return -EINVAL; in ddr_perf_event_add()
546 writel(cfg1, pmu->base + COUNTER_DPCR1); in ddr_perf_event_add()
550 counter = ddr_perf_alloc_counter(pmu, cfg); in ddr_perf_event_add()
552 dev_dbg(pmu->dev, "There are not enough counters\n"); in ddr_perf_event_add()
553 return -EOPNOTSUPP; in ddr_perf_event_add()
556 pmu->events[counter] = event; in ddr_perf_event_add()
557 hwc->idx = counter; in ddr_perf_event_add()
559 hwc->state |= PERF_HES_STOPPED; in ddr_perf_event_add()
569 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_event_stop() local
570 struct hw_perf_event *hwc = &event->hw; in ddr_perf_event_stop()
571 int counter = hwc->idx; in ddr_perf_event_stop()
573 ddr_perf_counter_enable(pmu, event->attr.config, counter, false); in ddr_perf_event_stop()
576 if (!--pmu->active_counter) in ddr_perf_event_stop()
577 ddr_perf_counter_enable(pmu, EVENT_CYCLES_ID, in ddr_perf_event_stop()
580 hwc->state |= PERF_HES_STOPPED; in ddr_perf_event_stop()
585 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_event_del() local
586 struct hw_perf_event *hwc = &event->hw; in ddr_perf_event_del()
587 int counter = hwc->idx; in ddr_perf_event_del()
591 ddr_perf_free_counter(pmu, counter); in ddr_perf_event_del()
592 hwc->idx = -1; in ddr_perf_event_del()
595 static void ddr_perf_pmu_enable(struct pmu *pmu) in ddr_perf_pmu_enable() argument
599 static void ddr_perf_pmu_disable(struct pmu *pmu) in ddr_perf_pmu_disable() argument
603 static int ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base, in ddr_perf_init() argument
606 *pmu = (struct ddr_pmu) { in ddr_perf_init()
607 .pmu = (struct pmu) { in ddr_perf_init()
625 pmu->id = ida_alloc(&ddr_ida, GFP_KERNEL); in ddr_perf_init()
626 return pmu->id; in ddr_perf_init()
632 struct ddr_pmu *pmu = (struct ddr_pmu *) p; in ddr_perf_irq_handler() local
636 ddr_perf_counter_enable(pmu, in ddr_perf_irq_handler()
654 if (!pmu->events[i]) in ddr_perf_irq_handler()
657 event = pmu->events[i]; in ddr_perf_irq_handler()
662 ddr_perf_counter_enable(pmu, in ddr_perf_irq_handler()
672 struct ddr_pmu *pmu = hlist_entry_safe(node, struct ddr_pmu, node); in ddr_perf_offline_cpu() local
675 if (cpu != pmu->cpu) in ddr_perf_offline_cpu()
682 perf_pmu_migrate_context(&pmu->pmu, cpu, target); in ddr_perf_offline_cpu()
683 pmu->cpu = target; in ddr_perf_offline_cpu()
685 WARN_ON(irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu))); in ddr_perf_offline_cpu()
692 struct ddr_pmu *pmu; in ddr_perf_probe() local
704 np = pdev->dev.of_node; in ddr_perf_probe()
706 pmu = devm_kzalloc(&pdev->dev, sizeof(*pmu), GFP_KERNEL); in ddr_perf_probe()
707 if (!pmu) in ddr_perf_probe()
708 return -ENOMEM; in ddr_perf_probe()
710 num = ddr_perf_init(pmu, base, &pdev->dev); in ddr_perf_probe()
712 platform_set_drvdata(pdev, pmu); in ddr_perf_probe()
714 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, DDR_PERF_DEV_NAME "%d", in ddr_perf_probe()
717 ret = -ENOMEM; in ddr_perf_probe()
721 pmu->devtype_data = of_device_get_match_data(&pdev->dev); in ddr_perf_probe()
723 pmu->cpu = raw_smp_processor_id(); in ddr_perf_probe()
730 dev_err(&pdev->dev, "cpuhp_setup_state_multi failed\n"); in ddr_perf_probe()
734 pmu->cpuhp_state = ret; in ddr_perf_probe()
736 /* Register the pmu instance for cpu hotplug */ in ddr_perf_probe()
737 ret = cpuhp_state_add_instance_nocalls(pmu->cpuhp_state, &pmu->node); in ddr_perf_probe()
739 dev_err(&pdev->dev, "Error %d registering hotplug\n", ret); in ddr_perf_probe()
746 dev_err(&pdev->dev, "Failed to get irq: %d", irq); in ddr_perf_probe()
751 ret = devm_request_irq(&pdev->dev, irq, in ddr_perf_probe()
755 pmu); in ddr_perf_probe()
757 dev_err(&pdev->dev, "Request irq failed: %d", ret); in ddr_perf_probe()
761 pmu->irq = irq; in ddr_perf_probe()
762 ret = irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu)); in ddr_perf_probe()
764 dev_err(pmu->dev, "Failed to set interrupt affinity!\n"); in ddr_perf_probe()
768 ret = perf_pmu_register(&pmu->pmu, name, -1); in ddr_perf_probe()
775 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node); in ddr_perf_probe()
777 cpuhp_remove_multi_state(pmu->cpuhp_state); in ddr_perf_probe()
779 ida_free(&ddr_ida, pmu->id); in ddr_perf_probe()
780 dev_warn(&pdev->dev, "i.MX8 DDR Perf PMU failed (%d), disabled\n", ret); in ddr_perf_probe()
786 struct ddr_pmu *pmu = platform_get_drvdata(pdev); in ddr_perf_remove() local
788 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node); in ddr_perf_remove()
789 cpuhp_remove_multi_state(pmu->cpuhp_state); in ddr_perf_remove()
791 perf_pmu_unregister(&pmu->pmu); in ddr_perf_remove()
793 ida_free(&ddr_ida, pmu->id); in ddr_perf_remove()
799 .name = "imx-ddr-pmu",