282 	int dtm;  member
1392 	struct arm_cmn_dtm *dtm = NULL;  in arm_cmn_read_dtm()  local
1399 		if (dtm != &cmn->dtms[dn->dtm]) {  in arm_cmn_read_dtm()
1400 			dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset;  in arm_cmn_read_dtm()
1401 			reg = readq_relaxed(dtm->base + offset);  in arm_cmn_read_dtm()
1598 		int wp_idx, dtm = dn->dtm, sel = hw->filter_sel;  in arm_cmn_val_add_event()  local
1600 		val->dtm_count[dtm]++;  in arm_cmn_val_add_event()
1603 			val->occupid[dtm][sel] = CMN_EVENT_OCCUPID(event) + 1;  in arm_cmn_val_add_event()
1609 		val->wp[dtm][wp_idx] = CMN_EVENT_WP_COMBINE(event) + 1;  in arm_cmn_val_add_event()
1646 		int wp_idx, wp_cmb, dtm = dn->dtm, sel = hw->filter_sel;  in arm_cmn_validate_group()  local
1648 		if (val->dtm_count[dtm] == CMN_DTM_NUM_COUNTERS)  in arm_cmn_validate_group()
1651 		if (sel > SEL_NONE && val->occupid[dtm][sel] &&  in arm_cmn_validate_group()
1652 		    val->occupid[dtm][sel] != CMN_EVENT_OCCUPID(event) + 1)  in arm_cmn_validate_group()
1659 		if (val->wp[dtm][wp_idx])  in arm_cmn_validate_group()
1662 		wp_cmb = val->wp[dtm][wp_idx ^ 1];  in arm_cmn_validate_group()
1770 		struct arm_cmn_dtm *dtm = &cmn->dtms[hw->dn[i].dtm] + hw->dtm_offset;  in arm_cmn_event_clear()  local
1774 			dtm->wp_event[arm_cmn_wp_idx(event)] = -1;  in arm_cmn_event_clear()
1779 		dtm->pmu_config_low &= ~CMN__PMEVCNT_PAIRED(dtm_idx);  in arm_cmn_event_clear()
1780 		writel_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG);  in arm_cmn_event_clear()
1822 		struct arm_cmn_dtm *dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset;  in arm_cmn_event_add()  local
1827 		while (dtm->pmu_config_low & CMN__PMEVCNT_PAIRED(dtm_idx))  in arm_cmn_event_add()
1837 			if (dtm->wp_event[wp_idx] >= 0)  in arm_cmn_event_add()
1840 			tmp = dtm->wp_event[wp_idx ^ 1];  in arm_cmn_event_add()
1846 			dtm->wp_event[wp_idx] = dtc_idx;  in arm_cmn_event_add()
1847 			writel_relaxed(cfg, dtm->base + CMN_DTM_WPn_CONFIG(wp_idx));  in arm_cmn_event_add()
1863 		dtm->input_sel[dtm_idx] = input_sel;  in arm_cmn_event_add()
1865 		dtm->pmu_config_low &= ~(CMN__PMEVCNT0_GLOBAL_NUM << shift);  in arm_cmn_event_add()
1866 		dtm->pmu_config_low |= FIELD_PREP(CMN__PMEVCNT0_GLOBAL_NUM, dtc_idx) << shift;  in arm_cmn_event_add()
1867 		dtm->pmu_config_low |= CMN__PMEVCNT_PAIRED(dtm_idx);  in arm_cmn_event_add()
1868 		reg = (u64)le32_to_cpu(dtm->pmu_config_high) << 32 | dtm->pmu_config_low;  in arm_cmn_event_add()
1869 		writeq_relaxed(reg, dtm->base + CMN_DTM_PMU_CONFIG);  in arm_cmn_event_add()
2029 static void arm_cmn_init_dtm(struct arm_cmn_dtm *dtm, struct arm_cmn_node *xp, int idx)  in arm_cmn_init_dtm()  argument
2033 	dtm->base = xp->pmu_base + CMN_DTM_OFFSET(idx);  in arm_cmn_init_dtm()
2034 	dtm->pmu_config_low = CMN_DTM_PMU_CONFIG_PMU_EN;  in arm_cmn_init_dtm()
2035 	writeq_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG);  in arm_cmn_init_dtm()
2037 		dtm->wp_event[i] = -1;  in arm_cmn_init_dtm()
2038 		writeq_relaxed(0, dtm->base + CMN_DTM_WPn_MASK(i));  in arm_cmn_init_dtm()
2039 		writeq_relaxed(~0ULL, dtm->base + CMN_DTM_WPn_VAL(i));  in arm_cmn_init_dtm()
2092 		dn->dtm = xp->dtm;  in arm_cmn_init_dtcs()
2094 			dn->dtm += arm_cmn_nid(cmn, dn->id).port / 2;  in arm_cmn_init_dtcs()
2159 	struct arm_cmn_dtm *dtm;  in arm_cmn_discover()  local
2226 	dtm = devm_kcalloc(cmn->dev, i, sizeof(*dtm), GFP_KERNEL);  in arm_cmn_discover()
2227 	if (!dtm)  in arm_cmn_discover()
2232 	cmn->dtms = dtm;  in arm_cmn_discover()
2253 		xp->dtm = dtm - cmn->dtms;  in arm_cmn_discover()
2254 		arm_cmn_init_dtm(dtm++, xp, 0);  in arm_cmn_discover()
2267 			arm_cmn_init_dtm(dtm++, xp, 1);  in arm_cmn_discover()
2269 			arm_cmn_init_dtm(dtm++, xp, 2);  in arm_cmn_discover()
2354 	sz = (void *)dtm - (void *)cmn->dtms;  in arm_cmn_discover()
2355 	dtm = devm_krealloc(cmn->dev, cmn->dtms, sz, GFP_KERNEL);  in arm_cmn_discover()
2356 	if (dtm)  in arm_cmn_discover()
2357 		cmn->dtms = dtm;  in arm_cmn_discover()