Lines Matching +full:0 +full:x94
35 #define O2_MUX_CONTROL 0x90 /* 32 bit */
36 #define O2_MUX_RING_OUT 0x0000000f
37 #define O2_MUX_SKTB_ACTV 0x000000f0
38 #define O2_MUX_SCTA_ACTV_ENA 0x00000100
39 #define O2_MUX_SCTB_ACTV_ENA 0x00000200
40 #define O2_MUX_SER_IRQ_ROUTE 0x0000e000
41 #define O2_MUX_SER_PCI 0x00010000
43 #define O2_MUX_SKTA_TURBO 0x000c0000 /* for 6833, 6860 */
44 #define O2_MUX_SKTB_TURBO 0x00300000
45 #define O2_MUX_AUX_VCC_3V 0x00400000
46 #define O2_MUX_PCI_VCC_5V 0x00800000
47 #define O2_MUX_PME_MUX 0x0f000000
51 #define O2_MODE_A 0x38
52 #define O2_MODE_A_2 0x26 /* for 6833B, 6860C */
53 #define O2_MODE_A_CD_PULSE 0x04
54 #define O2_MODE_A_SUSP_EDGE 0x08
55 #define O2_MODE_A_HOST_SUSP 0x10
56 #define O2_MODE_A_PWR_MASK 0x60
57 #define O2_MODE_A_QUIET 0x80
59 #define O2_MODE_B 0x39
60 #define O2_MODE_B_2 0x2e /* for 6833B, 6860C */
61 #define O2_MODE_B_IDENT 0x03
62 #define O2_MODE_B_ID_BSTEP 0x00
63 #define O2_MODE_B_ID_CSTEP 0x01
64 #define O2_MODE_B_ID_O2 0x02
65 #define O2_MODE_B_VS1 0x04
66 #define O2_MODE_B_VS2 0x08
67 #define O2_MODE_B_IRQ15_RI 0x80
69 #define O2_MODE_C 0x3a
70 #define O2_MODE_C_DREQ_MASK 0x03
71 #define O2_MODE_C_DREQ_INPACK 0x01
72 #define O2_MODE_C_DREQ_WP 0x02
73 #define O2_MODE_C_DREQ_BVD2 0x03
74 #define O2_MODE_C_ZVIDEO 0x08
75 #define O2_MODE_C_IREQ_SEL 0x30
76 #define O2_MODE_C_MGMT_SEL 0xc0
78 #define O2_MODE_D 0x3b
79 #define O2_MODE_D_IRQ_MODE 0x03
80 #define O2_MODE_D_PCI_CLKRUN 0x04
81 #define O2_MODE_D_CB_CLKRUN 0x08
82 #define O2_MODE_D_SKT_ACTV 0x20
83 #define O2_MODE_D_PCI_FIFO 0x40 /* for OZ6729, OZ6730 */
84 #define O2_MODE_D_W97_IRQ 0x40
85 #define O2_MODE_D_ISA_IRQ 0x80
87 #define O2_MHPG_DMA 0x3c
88 #define O2_MHPG_CHANNEL 0x07
89 #define O2_MHPG_CINT_ENA 0x08
90 #define O2_MHPG_CSC_ENA 0x10
92 #define O2_FIFO_ENA 0x3d
93 #define O2_FIFO_ZVIDEO_3 0x08
94 #define O2_FIFO_PCI_FIFO 0x10
95 #define O2_FIFO_POSTWR 0x40
96 #define O2_FIFO_BUFFER 0x80
98 #define O2_MODE_E 0x3e
99 #define O2_MODE_E_MHPG_DMA 0x01
100 #define O2_MODE_E_SPKR_OUT 0x02
101 #define O2_MODE_E_LED_OUT 0x08
102 #define O2_MODE_E_SKTA_ACTV 0x10
104 #define O2_RESERVED1 0x94
105 #define O2_RESERVED2 0xD4
106 #define O2_RES_READ_PREFETCH 0x02
107 #define O2_RES_WRITE_BURST 0x08
112 * 'reserved' register at 0x94/D4. allows setting read prefetch and write in o2micro_override()
114 * working. for some bridges it is at 0x94, for others at 0xD4. it's in o2micro_override()
121 if (PCI_FUNC(socket->dev->devfn) == 0) { in o2micro_override()
124 dev_dbg(&socket->dev->dev, "O2: 0x94/0xD4: %02x/%02x\n", a, b); in o2micro_override()
146 if (strcasecmp(o2_speedup, "on") == 0) in o2micro_override()
148 else if (strcasecmp(o2_speedup, "off") == 0) in o2micro_override()
150 else if (strcasecmp(o2_speedup, "default") != 0) in o2micro_override()
171 return 0; in o2micro_override()