Lines Matching +full:test +full:- +full:manual +full:- +full:mr
1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
5 * should be handled in arch-specific code.
20 #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */
88 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) in pcie_failed_link_retrain()
95 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); in pcie_failed_link_retrain()
157 if ((f->class == (u32) (dev->class >> f->class_shift) || in pci_do_fixups()
158 f->class == (u32) PCI_ANY_ID) && in pci_do_fixups()
159 (f->vendor == dev->vendor || in pci_do_fixups()
160 f->vendor == (u16) PCI_ANY_ID) && in pci_do_fixups()
161 (f->device == dev->device || in pci_do_fixups()
162 f->device == (u16) PCI_ANY_ID)) { in pci_do_fixups()
165 hook = offset_to_ptr(&f->hook_offset); in pci_do_fixups()
167 hook = f->hook; in pci_do_fixups()
293 * key system devices. For devices that need to have mmio decoding always-on,
294 * we need to set the dev->mmio_always_on bit.
298 dev->mmio_always_on = 1; in quirk_mmio_always_on()
339 * contacts at VIA ask them for me please -- Alan
386 /* Chipsets where PCI->PCI transfers vanish or hang */
424 * Made according to a Windows driver-based patch by George E. Breese;
426 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
427 * which Mr Breese based his work.
445 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; in quirk_vialatency()
449 if (p->revision < 0x40 || p->revision > 0x42) in quirk_vialatency()
457 if (p->revision < 0x10 || p->revision > 0x12) in quirk_vialatency()
549 dev->cfg_size = 0xA0; in quirk_citrine()
559 dev->cfg_size = 0x600; in quirk_nfp6000()
572 struct resource *r = &dev->resource[i]; in quirk_extend_bar_to_page()
574 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { in quirk_extend_bar_to_page()
575 r->end = PAGE_SIZE - 1; in quirk_extend_bar_to_page()
576 r->start = 0; in quirk_extend_bar_to_page()
577 r->flags |= IORESOURCE_UNSET; in quirk_extend_bar_to_page()
587 * If it's needed, re-allocate the region.
591 struct resource *r = &dev->resource[0]; in quirk_s3_64M()
593 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { in quirk_s3_64M()
594 r->flags |= IORESOURCE_UNSET; in quirk_s3_64M()
595 r->start = 0; in quirk_s3_64M()
596 r->end = 0x3ffffff; in quirk_s3_64M()
607 struct resource *res = dev->resource + pos; in quirk_io()
614 res->name = pci_name(dev); in quirk_io()
615 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; in quirk_io()
616 res->flags |= in quirk_io()
618 region &= ~(size - 1); in quirk_io()
622 bus_region.end = region + size - 1; in quirk_io()
623 pcibios_bus_to_resource(dev->bus, res, &bus_region); in quirk_io()
635 * CS553x's ISA PCI BARs may also be read-only (ref:
636 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
657 struct resource *res = dev->resource + nr; in quirk_io_region()
660 region &= ~(size - 1); in quirk_io_region()
665 res->name = pci_name(dev); in quirk_io_region()
666 res->flags = IORESOURCE_IO; in quirk_io_region()
670 bus_region.end = region + size - 1; in quirk_io_region()
671 pcibios_bus_to_resource(dev->bus, res, &bus_region); in quirk_io_region()
679 * between 0x3b0->0x3bb or read 0x3d3
703 u32 class = pdev->class; in quirk_amd_nl_class()
706 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; in quirk_amd_nl_class()
707 …pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhc… in quirk_amd_nl_class()
708 class, pdev->class); in quirk_amd_nl_class()
716 * devices should use dwc3-haps driver. Change these devices' class code to
717 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
722 u32 class = pdev->class; in quirk_synopsys_haps()
724 switch (pdev->device) { in quirk_synopsys_haps()
728 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; in quirk_synopsys_haps()
729 …pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhc… in quirk_synopsys_haps()
730 class, pdev->class); in quirk_synopsys_haps()
777 base &= -size; in piix4_io_quirk()
778 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); in piix4_io_quirk()
803 base &= -size; in piix4_mem_quirk()
804 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); in piix4_mem_quirk()
856 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
930 base &= ~(size-1); in ich6_lpc_generic_decode()
936 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); in ich6_lpc_generic_decode()
944 /* ICH6-specific generic IO decode */ in quirk_ich6_lpc()
963 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ in ich7_lpc_generic_decode()
975 /* ICH7-10 has the same common LPC generic IO decode registers */
1007 if (dev->revision & 0x10) in quirk_vt82c586_acpi()
1024 "vt82c686 HW-mon"); in quirk_vt82c686_acpi()
1043 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
1044 * back-to-back: Disable fast back-to-back on the secondary bus segment
1051 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); in quirk_xio2000a()
1052 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { in quirk_xio2000a()
1066 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
1069 * TODO: When we have device-specific interrupt routers, this code will go
1079 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ in quirk_via_ioapic()
1091 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
1103 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); in quirk_via_vt8237_bypass_apic_deassert()
1111 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1121 if (dev->revision >= 0x02) { in quirk_amd_ioapic()
1133 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ in quirk_cavium_sriov_rnm_link()
1134 if (dev->subsystem_device == 0xa118) in quirk_cavium_sriov_rnm_link()
1135 dev->sriov->link = dev->devfn; in quirk_cavium_sriov_rnm_link()
1142 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1146 if (dev->subordinate && dev->revision <= 0x12) { in quirk_amd_8131_mmrbc()
1147 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", in quirk_amd_8131_mmrbc()
1148 dev->revision); in quirk_amd_8131_mmrbc()
1149 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; in quirk_amd_8131_mmrbc()
1159 * -jgarzik
1169 d->irq = irq; in quirk_via_acpi()
1175 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1180 switch (dev->device) { in quirk_via_bridge()
1187 via_vlink_dev_lo = PCI_SLOT(dev->devfn); in quirk_via_bridge()
1188 via_vlink_dev_hi = PCI_SLOT(dev->devfn); in quirk_via_bridge()
1215 * quirk_via_vlink - VIA VLink IRQ number update
1230 if (via_vlink_dev_lo == -1) in quirk_via_vlink()
1233 new_irq = dev->irq; in quirk_via_vlink()
1240 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || in quirk_via_vlink()
1241 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) in quirk_via_vlink()
1266 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); in quirk_vt82c598_id()
1309 * DreamWorks-provided workaround for Dunord I-3000 problem
1317 struct resource *r = &dev->resource[1]; in quirk_dunord()
1319 r->flags |= IORESOURCE_UNSET; in quirk_dunord()
1320 r->start = 0; in quirk_dunord()
1321 r->end = 0xffffff; in quirk_dunord()
1326 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1328 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1332 dev->transparent = 1; in quirk_transparent_bridge()
1367 if (pdev->revision != 0x04) /* Only C0 requires this */ in quirk_disable_pxb()
1381 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ in quirk_amd_ide_mode()
1392 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; in quirk_amd_ide_mode()
1412 pdev->class &= ~5; in quirk_svwks_csb5ide()
1419 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1429 pdev->class &= ~5; in quirk_ide_samemode()
1438 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; in quirk_no_ata_d3()
1454 * This was originally an Alpha-specific thing, but it really fits here.
1455 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1459 dev->class = PCI_CLASS_BRIDGE_EISA << 8; in quirk_eisa_bridge()
1472 * becomes necessary to do this tweak in two steps -- the chosen trigger
1473 * is either the Host bridge (preferred) or on-board VGA controller.
1486 * the DSDT and double-check that there is no code accessing the SMBus.
1492 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { in asus_hides_smbus_hostbridge()
1493 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) in asus_hides_smbus_hostbridge()
1494 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1495 case 0x8025: /* P4B-LX */ in asus_hides_smbus_hostbridge()
1501 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) in asus_hides_smbus_hostbridge()
1502 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1503 case 0x80b1: /* P4GE-V */ in asus_hides_smbus_hostbridge()
1505 case 0x8093: /* P4B533-V */ in asus_hides_smbus_hostbridge()
1508 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) in asus_hides_smbus_hostbridge()
1509 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1513 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) in asus_hides_smbus_hostbridge()
1514 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1518 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) in asus_hides_smbus_hostbridge()
1519 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1520 case 0x80c9: /* PU-DLS */ in asus_hides_smbus_hostbridge()
1523 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) in asus_hides_smbus_hostbridge()
1524 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1530 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1531 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1536 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) in asus_hides_smbus_hostbridge()
1537 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1538 case 0x80f2: /* P4P800-X */ in asus_hides_smbus_hostbridge()
1541 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) in asus_hides_smbus_hostbridge()
1542 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1547 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { in asus_hides_smbus_hostbridge()
1548 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1549 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1554 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) in asus_hides_smbus_hostbridge()
1555 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1561 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) in asus_hides_smbus_hostbridge()
1562 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1566 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { in asus_hides_smbus_hostbridge()
1567 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1568 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1572 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { in asus_hides_smbus_hostbridge()
1573 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1574 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1578 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) in asus_hides_smbus_hostbridge()
1579 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1580 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ in asus_hides_smbus_hostbridge()
1583 * its on-board VGA controller */ in asus_hides_smbus_hostbridge()
1586 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) in asus_hides_smbus_hostbridge()
1587 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1592 * subvendor/subdevice IDs and on-board VGA in asus_hides_smbus_hostbridge()
1598 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) in asus_hides_smbus_hostbridge()
1599 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1603 * its on-board VGA controller */ in asus_hides_smbus_hostbridge()
1755 dev->device = devid; in quirk_sis_503()
1765 * -- bjd
1772 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { in asus_hides_ac97_lpc()
1773 if (dev->device == PCI_DEVICE_ID_VIA_8237) in asus_hides_ac97_lpc()
1806 if (PCI_FUNC(pdev->devfn)) in quirk_jmicron_ata()
1812 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ in quirk_jmicron_ata()
1815 switch (pdev->device) { in quirk_jmicron_ata()
1847 pdev->hdr_type = hdr & 0x7f; in quirk_jmicron_ata()
1848 pdev->multifunction = !!(hdr & 0x80); in quirk_jmicron_ata()
1851 pdev->class = class >> 8; in quirk_jmicron_ata()
1876 if (dev->multifunction) { in quirk_jmicron_async_suspend()
1877 device_disable_async_suspend(&dev->dev); in quirk_jmicron_async_suspend()
1878 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); in quirk_jmicron_async_suspend()
1891 if ((pdev->class >> 8) != 0xff00) in quirk_alder_ioapic()
1895 * The first BAR is the location of the IO-APIC... we must in quirk_alder_ioapic()
1900 insert_resource(&iomem_resource, &pdev->resource[0]); in quirk_alder_ioapic()
1907 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); in quirk_alder_ioapic()
1915 dev->no_msi = 1; in quirk_no_msi()
1926 pdev->no_msi = 1; in quirk_pcie_mch()
1937 * SMMU stall feature, by setting dma-can-stall for ACPI platforms.
1940 * break the PCI requirement for free-flowing writes and may lead to
1942 * be fault-tolerant, so there's no ACPI binding to describe anything else,
1949 PROPERTY_ENTRY_BOOL("dma-can-stall"), in quirk_huawei_pcie_sva()
1953 if (pdev->revision != 0x21 && pdev->revision != 0x30) in quirk_huawei_pcie_sva()
1956 pdev->pasid_no_tlp = 1; in quirk_huawei_pcie_sva()
1959 * Set the dma-can-stall property on ACPI platforms. Device tree in quirk_huawei_pcie_sva()
1962 if (!pdev->dev.of_node && in quirk_huawei_pcie_sva()
1963 device_create_managed_software_node(&pdev->dev, properties, NULL)) in quirk_huawei_pcie_sva()
1975 * together on certain PXH-based systems.
1979 dev->no_msi = 1; in quirk_pcie_pxh()
1995 dev->no_d1d2 = 1; in quirk_intel_pcie_pm()
2021 if (dev->d3hot_delay >= delay) in quirk_d3hot_delay()
2024 dev->d3hot_delay = delay; in quirk_d3hot_delay()
2025 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", in quirk_d3hot_delay()
2026 dev->d3hot_delay); in quirk_d3hot_delay()
2031 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && in quirk_radeon_pm()
2032 dev->subsystem_device == 0x00e2) in quirk_radeon_pm()
2038 * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus
2056 * remain on in D3hot state. The D3hot-to-D0 transition then requires an
2071 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); in dmi_disable_ioapicreroute()
2082 .ident = "ASUSTek Computer INC. M2N-LR",
2085 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
2103 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; in quirk_reroute_to_boot_interrupts_intel()
2105 dev->vendor, dev->device); in quirk_reroute_to_boot_interrupts_intel()
2130 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
2131 * 300641-004US, section 5.7.3.
2133 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
2134 * Core IO on Xeon E5 v2, see Intel order no 329188-003.
2135 * Core IO on Xeon E7 v2, see Intel order no 329595-002.
2136 * Core IO on Xeon E5 v3, see Intel order no 330784-003.
2137 * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
2138 * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
2139 * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
2140 * Core IO on Xeon D-1500, see Intel order no 332051-001.
2157 switch (dev->device) { in quirk_disable_intel_boot_interrupt()
2168 case 0x6f28: /* Xeon D-1500 */ in quirk_disable_intel_boot_interrupt()
2180 dev->vendor, dev->device); in quirk_disable_intel_boot_interrupt()
2183 * Device 29 Func 5 Device IDs of IO-APIC
2219 /* Disable boot interrupts on HT-1000 */
2245 dev->vendor, dev->device); in quirk_disable_broadcom_boot_interrupt()
2254 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2268 if ((dev->revision == AMD_813X_REV_B1) || in quirk_disable_amd_813x_boot_interrupt()
2269 (dev->revision == AMD_813X_REV_B2)) in quirk_disable_amd_813x_boot_interrupt()
2277 dev->vendor, dev->device); in quirk_disable_amd_813x_boot_interrupt()
2296 dev->vendor, dev->device); in quirk_disable_amd_8111_boot_interrupt()
2301 dev->vendor, dev->device); in quirk_disable_amd_8111_boot_interrupt()
2308 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2310 * Re-allocate the region if needed...
2314 struct resource *r = &dev->resource[0]; in quirk_tc86c001_ide()
2316 if (r->start & 0x8) { in quirk_tc86c001_ide()
2317 r->flags |= IORESOURCE_UNSET; in quirk_tc86c001_ide()
2318 r->start = 0; in quirk_tc86c001_ide()
2319 r->end = 0xf; in quirk_tc86c001_ide()
2331 * Re-allocate the regions to a 256-byte boundary if necessary.
2338 if (dev->revision >= 2) in quirk_plx_pci9050()
2343 struct resource *r = &dev->resource[bar]; in quirk_plx_pci9050()
2344 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", in quirk_plx_pci9050()
2346 r->flags |= IORESOURCE_UNSET; in quirk_plx_pci9050()
2347 r->start = 0; in quirk_plx_pci9050()
2348 r->end = 0xff; in quirk_plx_pci9050()
2367 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; in quirk_netmos()
2368 unsigned int num_serial = dev->subsystem_device & 0xf; in quirk_netmos()
2380 switch (dev->device) { in quirk_netmos()
2383 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && in quirk_netmos()
2384 dev->subsystem_device == 0x0299) in quirk_netmos()
2393 dev->device, num_parallel, num_serial); in quirk_netmos()
2394 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | in quirk_netmos()
2395 (dev->class & 0xff); in quirk_netmos()
2408 switch (dev->device) { in quirk_e100_interrupt()
2433 * re-enable them when it's ready. in quirk_e100_interrupt()
2444 if (dev->pm_cap) { in quirk_e100_interrupt()
2445 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in quirk_e100_interrupt()
2499 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2506 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2515 dev->clear_retrain_link = 1; in quirk_enable_clear_retrain_link()
2524 u32 class = dev->class; in fixup_rev1_53c810()
2533 dev->class = PCI_CLASS_STORAGE_SCSI << 8; in fixup_rev1_53c810()
2534 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", in fixup_rev1_53c810()
2535 class, dev->class); in fixup_rev1_53c810()
2548 dev->io_window_1k = 1; in quirk_p64h2_1k_io()
2582 * VT6212L is found -- the CX700 core itself also contains a USB in quirk_via_cx700_pci_parking_caching()
2592 * p should contain the first (internal) VT6212L -- see if we have in quirk_via_cx700_pci_parking_caching()
2614 /* Set PCI Master Bus time-out to "1x16 PCLK" */ in quirk_via_cx700_pci_parking_caching()
2646 * DRBs - this is where we expose device 6.
2647 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2689 if (dev->subordinate) { in quirk_disable_msi()
2691 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in quirk_disable_msi()
2708 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); in quirk_amd_780_apc_msi()
2710 if (apc_bridge->device == 0x9602) in quirk_amd_780_apc_msi()
2727 while (pos && ttl--) { in msi_ht_cap_enabled()
2765 pdev = pci_get_slot(dev->bus, 0); in quirk_nvidia_ck804_msi_ht_cap()
2781 while (pos && ttl--) { in ht_enable_msi_mapping()
2802 * The P5N32-SLI motherboards from Asus have a problem with MSI
2811 (strstr(board_name, "P5N32-SLI PREMIUM") || in nvenet_msi_disable()
2812 strstr(board_name, "P5N32-E SLI"))) { in nvenet_msi_disable()
2813 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); in nvenet_msi_disable()
2814 dev->no_msi = 1; in nvenet_msi_disable()
2822 * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device
2827 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2832 dev->no_msi = 1; in pci_quirk_nvidia_tegra_disable_rp_msi()
2922 while (pos && ttl--) { in ht_check_msi_mapping()
2950 dev_no = host_bridge->devfn >> 3; in host_bridge_with_leaf()
2952 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); in host_bridge_with_leaf()
3008 dev_no = dev->devfn >> 3; in nv_ht_enable_msi_mapping()
3009 for (i = dev_no; i >= 0; i--) { in nv_ht_enable_msi_mapping()
3010 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); in nv_ht_enable_msi_mapping()
3045 while (pos && ttl--) { in ht_disable_msi_mapping()
3078 * a non-HyperTransport host bridge. Locate the host bridge. in __nv_msi_ht_cap_quirk()
3080 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, in __nv_msi_ht_cap_quirk()
3127 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_bug()
3144 if ((p->revision < 0x3B) && (p->revision >= 0x30)) in quirk_msi_intx_disable_ati_bug()
3145 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_ati_bug()
3152 if (dev->revision < 0x18) { in quirk_msi_intx_disable_qca_bug()
3154 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_qca_bug()
3218 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3222 * tested), since currently there is no standard way to disable only MSI-X.
3229 dev->no_msi = 1; in quirk_al_msi_disable()
3230 pci_warn(dev, "Disabling MSI/MSI-X\n"); in quirk_al_msi_disable()
3237 * Allow manual resource allocation for PCI hotplug bridges via
3238 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3245 dev->is_hotplug_bridge = 1; in quirk_hotplug_bridge()
3262 * MMC controller - so the SDHCI driver never sees them.
3286 if (PCI_FUNC(dev->devfn)) in ricoh_mmc_fixup_rl5c476()
3317 if (PCI_FUNC(dev->devfn)) in ricoh_mmc_fixup_r5c832()
3324 * 0x150 - SD2.0 mode enable for changing base clock in ricoh_mmc_fixup_r5c832()
3326 * 0xe1 - Base clock frequency in ricoh_mmc_fixup_r5c832()
3327 * 0x32 - 50Mhz new clock frequency in ricoh_mmc_fixup_r5c832()
3328 * 0xf9 - Key register for 0x150 in ricoh_mmc_fixup_r5c832()
3329 * 0xfc - key register for 0xe1 in ricoh_mmc_fixup_r5c832()
3331 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || in ricoh_mmc_fixup_r5c832()
3332 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { in ricoh_mmc_fixup_r5c832()
3369 * This is a quirk for masking VT-d spec-defined errors to platform error
3372 * on the RAS config settings of the platform) when a VT-d fault happens.
3375 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3391 u32 class = dev->class; in fixup_ti816x_class()
3394 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; in fixup_ti816x_class()
3395 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", in fixup_ti816x_class()
3396 class, dev->class); in fixup_ti816x_class()
3407 dev->pcie_mpss = 1; /* 256 bytes */ in fixup_mpss_256()
3422 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3458 /* Intel 5000 series memory controllers and ports 2-7 */
3473 /* Intel 5100 series memory controllers and ports 2-7 */
3500 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; in quirk_intel_ntb()
3506 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; in quirk_intel_ntb()
3515 * and the interrupt ends up -somewhere-.
3555 dev->d3hot_delay = 0; in quirk_remove_d3hot_delay()
3561 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
3591 dev->broken_intx_masking = 1; in quirk_broken_intx_masking()
3604 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3611 * DisINTx can be set but the interrupt status bit is non-functional.
3651 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3667 if (pdev->device == mellanox_broken_intx_devs[i]) { in mellanox_check_broken_intx_masking()
3668 pdev->broken_intx_masking = 1; in mellanox_check_broken_intx_masking()
3674 * Getting here means Connect-IB cards and up. Connect-IB has no INTx in mellanox_check_broken_intx_masking()
3677 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) in mellanox_check_broken_intx_masking()
3680 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && in mellanox_check_broken_intx_masking()
3681 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) in mellanox_check_broken_intx_masking()
3684 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ in mellanox_check_broken_intx_masking()
3692 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); in mellanox_check_broken_intx_masking()
3704 …pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW… in mellanox_check_broken_intx_masking()
3705 fw_major, fw_minor, fw_subminor, pdev->device == in mellanox_check_broken_intx_masking()
3707 pdev->broken_intx_masking = 1; in mellanox_check_broken_intx_masking()
3720 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; in quirk_no_bus_reset()
3729 if ((dev->device & 0xffc0) == 0x2340) in quirk_nvidia_no_bus_reset()
3737 * The device will throw a Link Down error on AER-capable systems and
3772 if (!pci_is_root_bus(dev->bus)) in quirk_no_pm_reset()
3773 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; in quirk_no_pm_reset()
3777 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3778 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3794 if (pdev->is_hotplug_bridge && in quirk_thunderbolt_hotplug_msi()
3795 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || in quirk_thunderbolt_hotplug_msi()
3796 pdev->revision <= 1)) in quirk_thunderbolt_hotplug_msi()
3797 pdev->no_msi = 1; in quirk_thunderbolt_hotplug_msi()
3844 bridge = ACPI_HANDLE(&dev->dev); in quirk_apple_poweroff_thunderbolt()
3875 * Following are device-specific reset methods which can be used to
3876 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3882 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf in reset_intel_82599_sfp_virtfn()
3912 return -ENOMEM; in reset_ivb_igd()
3943 /* Device-specific reset method for Chelsio T4-based adapters */
3950 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating in reset_chelsio_generic_dev()
3951 * that we have no device-specific reset method. in reset_chelsio_generic_dev()
3953 if ((dev->device & 0xf000) != 0x4000) in reset_chelsio_generic_dev()
3954 return -ENOTTY; in reset_chelsio_generic_dev()
3980 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts in reset_chelsio_generic_dev()
3981 * are disabled when an MSI-X interrupt message needs to be delivered. in reset_chelsio_generic_dev()
3982 * So we briefly re-enable MSI-X interrupts for the duration of the in reset_chelsio_generic_dev()
3984 * MSI-X state. in reset_chelsio_generic_dev()
3986 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); in reset_chelsio_generic_dev()
3988 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, in reset_chelsio_generic_dev()
4011 * FLR where config space reads from the device return -1. We seem to be
4028 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || in nvme_disable_and_flr()
4030 return -ENOTTY; in nvme_disable_and_flr()
4037 return -ENOTTY; in nvme_disable_and_flr()
4116 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */
4128 return -ENOTTY; in reset_hinic_vf_dev()
4134 return -ENOTTY; in reset_hinic_vf_dev()
4191 * These device-specific reset methods are here rather than in a driver
4199 for (i = pci_dev_reset_methods; i->reset; i++) { in pci_dev_specific_reset()
4200 if ((i->vendor == dev->vendor || in pci_dev_specific_reset()
4201 i->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_reset()
4202 (i->device == dev->device || in pci_dev_specific_reset()
4203 i->device == (u16)PCI_ANY_ID)) in pci_dev_specific_reset()
4204 return i->reset(dev, probe); in pci_dev_specific_reset()
4207 return -ENOTTY; in pci_dev_specific_reset()
4212 if (PCI_FUNC(dev->devfn) != 0) in quirk_dma_func0_alias()
4213 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); in quirk_dma_func0_alias()
4226 if (PCI_FUNC(dev->devfn) != 1) in quirk_dma_func1_alias()
4227 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); in quirk_dma_func1_alias()
4285 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4295 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4320 pci_add_dma_alias(dev, id->driver_data, 1); in quirk_fixed_dma_alias()
4325 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4327 * used as either forward or reverse bridges, so we need to test whether the
4329 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
4330 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4331 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4335 if (!pci_is_root_bus(pdev->bus) && in quirk_use_pcie_bridge_dma_alias()
4336 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && in quirk_use_pcie_bridge_dma_alias()
4337 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && in quirk_use_pcie_bridge_dma_alias()
4338 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) in quirk_use_pcie_bridge_dma_alias()
4339 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; in quirk_use_pcie_bridge_dma_alias()
4356 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4369 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4404 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; in quirk_bridge_cavm_thrx2_pcie_root()
4412 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4417 u32 class = pdev->class; in quirk_tw686x_class()
4420 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; in quirk_tw686x_class()
4421 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", in quirk_tw686x_class()
4422 class, pdev->class); in quirk_tw686x_class()
4440 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; in quirk_relaxedordering_disable()
4527 * If a non-compliant device generates a completion with a different
4529 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4533 * If the non-compliant device generates completions with zero attributes
4555 dev_name(&pdev->dev)); in quirk_disable_root_port_attributes()
4573 if ((pdev->device & 0xff00) == 0x5400) in quirk_chelsio_T5_disable_root_port_attributes()
4580 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4598 * AMD has indicated that the devices below do not support peer-to-peer
4601 * peer-to-peer between functions can claim to support a subset of ACS.
4629 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) in pci_quirk_amd_sb_acs()
4630 return -ENODEV; in pci_quirk_amd_sb_acs()
4635 return -ENODEV; in pci_quirk_amd_sb_acs()
4644 return -ENODEV; in pci_quirk_amd_sb_acs()
4653 switch (dev->device) { in pci_quirk_cavium_acs_match()
4670 return -ENOTTY; in pci_quirk_cavium_acs()
4687 * X-Gene Root Ports matching this quirk do not allow peer-to-peer in pci_quirk_xgene_acs()
4697 * But the implementation could block peer-to-peer transactions between them
4698 * and provide ACS-like functionality.
4705 return -ENOTTY; in pci_quirk_zhaoxin_pcie_ports_acs()
4707 switch (dev->device) { in pci_quirk_zhaoxin_pcie_ports_acs()
4719 * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4734 /* Lynxpoint-H PCH */
4737 /* Lynxpoint-LP PCH */
4756 /* Filter out a few obvious non-matches first */ in pci_quirk_intel_pch_acs_match()
4761 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) in pci_quirk_intel_pch_acs_match()
4770 return -ENOTTY; in pci_quirk_intel_pch_acs()
4772 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) in pci_quirk_intel_pch_acs()
4780 * These QCOM Root Ports do provide ACS-like features to disable peer
4784 * Hardware doesn't support peer-to-peer and each Root Port is a Root
4810 return -ENOTTY; in pci_quirk_al_acs()
4814 * but do include ACS-like functionality. The hardware doesn't support in pci_quirk_al_acs()
4815 * peer-to-peer transactions via the root port and each has a unique in pci_quirk_al_acs()
4835 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4836 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4844 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4848 * 0xa290-0xa29f PCI Express Root port #{0-16}
4849 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4855 * August 2017, Revision 002, Document#: 334660-002)[6]
4858 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4860 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4862 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4863 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4864 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4865 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4866 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4867 …ww.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-…
4868 …tel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datas…
4875 switch (dev->device) { in pci_quirk_intel_spt_pch_acs_match()
4893 return -ENOTTY; in pci_quirk_intel_spt_pch_acs()
4895 pos = dev->acs_cap; in pci_quirk_intel_spt_pch_acs()
4897 return -ENOTTY; in pci_quirk_intel_spt_pch_acs()
4914 * in their ACS capability if they support peer-to-peer transactions. in pci_quirk_mf_endpoint_acs()
4916 * perform peer-to-peer with other functions, allowing us to mask out in pci_quirk_mf_endpoint_acs()
4928 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, in pci_quirk_rciep_acs()
4929 * "Root-Complex Peer to Peer Considerations". in pci_quirk_rciep_acs()
4932 return -ENOTTY; in pci_quirk_rciep_acs()
4942 * they do not allow peer-to-peer transactions between Root Ports. in pci_quirk_brcm_acs()
4951 * Wangxun 10G/1G NICs have no ACS capability, and on multi-function
4952 * devices, peer-to-peer transactions are not be used between the functions.
4959 switch (dev->device) { in pci_quirk_wangxun_nic_acs()
5032 /* 82571 (Quads omitted due to non-ACS switch) */
5049 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
5050 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
5053 /* Cavium multi-function devices */
5057 /* APM X-Gene */
5068 /* Broadcom multi-function device */
5076 /* Zhaoxin multi-function devices */
5081 /* LX2xx0A : without security features + CAN-FD */
5085 /* LX2xx0C : security features + CAN-FD */
5097 /* LX2xx2A : without security features + CAN-FD */
5101 /* LX2xx2C : security features + CAN-FD */
5121 * pci_dev_specific_acs_enabled - check whether device provides ACS controls
5126 * -ENOTTY: No quirk applies to this device; we can't tell whether the
5138 * or control to indicate their support here. Multi-function express in pci_dev_specific_acs_enabled()
5139 * devices which do not allow internal peer-to-peer between functions, in pci_dev_specific_acs_enabled()
5142 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { in pci_dev_specific_acs_enabled()
5143 if ((i->vendor == dev->vendor || in pci_dev_specific_acs_enabled()
5144 i->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_acs_enabled()
5145 (i->device == dev->device || in pci_dev_specific_acs_enabled()
5146 i->device == (u16)PCI_ANY_ID)) { in pci_dev_specific_acs_enabled()
5147 ret = i->acs_enabled(dev, acs_flags); in pci_dev_specific_acs_enabled()
5153 return -ENOTTY; in pci_dev_specific_acs_enabled()
5165 /* Backbone Peer Non-Posted Disable */
5185 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), in pci_quirk_enable_intel_lpc_acs()
5188 return -EINVAL; in pci_quirk_enable_intel_lpc_acs()
5193 return -ENOMEM; in pci_quirk_enable_intel_lpc_acs()
5197 * therefore read-only. If both posted and non-posted peer cycles are in pci_quirk_enable_intel_lpc_acs()
5245 * if dev->external_facing || dev->untrusted
5250 return -ENOTTY; in pci_quirk_enable_intel_pch_acs()
5259 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; in pci_quirk_enable_intel_pch_acs()
5272 return -ENOTTY; in pci_quirk_enable_intel_spt_pch_acs()
5274 pos = dev->acs_cap; in pci_quirk_enable_intel_spt_pch_acs()
5276 return -ENOTTY; in pci_quirk_enable_intel_spt_pch_acs()
5286 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) in pci_quirk_enable_intel_spt_pch_acs()
5302 return -ENOTTY; in pci_quirk_disable_intel_spt_pch_acs_redir()
5304 pos = dev->acs_cap; in pci_quirk_disable_intel_spt_pch_acs_redir()
5306 return -ENOTTY; in pci_quirk_disable_intel_spt_pch_acs_redir()
5342 if ((p->vendor == dev->vendor || in pci_dev_specific_enable_acs()
5343 p->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_enable_acs()
5344 (p->device == dev->device || in pci_dev_specific_enable_acs()
5345 p->device == (u16)PCI_ANY_ID) && in pci_dev_specific_enable_acs()
5346 p->enable_acs) { in pci_dev_specific_enable_acs()
5347 ret = p->enable_acs(dev); in pci_dev_specific_enable_acs()
5353 return -ENOTTY; in pci_dev_specific_enable_acs()
5363 if ((p->vendor == dev->vendor || in pci_dev_specific_disable_acs_redir()
5364 p->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_disable_acs_redir()
5365 (p->device == dev->device || in pci_dev_specific_disable_acs_redir()
5366 p->device == (u16)PCI_ANY_ID) && in pci_dev_specific_disable_acs_redir()
5367 p->disable_acs_redir) { in pci_dev_specific_disable_acs_redir()
5368 ret = p->disable_acs_redir(dev); in pci_dev_specific_disable_acs_redir()
5374 return -ENOTTY; in pci_dev_specific_disable_acs_redir()
5392 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) in quirk_intel_qat_vf_cap()
5412 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() in quirk_intel_qat_vf_cap()
5425 pdev->pcie_cap = pos; in quirk_intel_qat_vf_cap()
5427 pdev->pcie_flags_reg = reg16; in quirk_intel_qat_vf_cap()
5429 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; in quirk_intel_qat_vf_cap()
5431 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; in quirk_intel_qat_vf_cap()
5434 pdev->cfg_size = PCI_CFG_SPACE_SIZE; in quirk_intel_qat_vf_cap()
5444 state->cap.cap_nr = PCI_CAP_ID_EXP; in quirk_intel_qat_vf_cap()
5445 state->cap.cap_extended = 0; in quirk_intel_qat_vf_cap()
5446 state->cap.size = size; in quirk_intel_qat_vf_cap()
5447 cap = (u16 *)&state->cap.data[0]; in quirk_intel_qat_vf_cap()
5455 hlist_add_head(&state->next, &pdev->saved_cap_space); in quirk_intel_qat_vf_cap()
5472 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; in quirk_no_flr()
5484 if (dev->revision == 0x1) in quirk_no_flr_snet()
5491 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); in quirk_no_ext_tags()
5496 bridge->no_ext_tags = 1; in quirk_no_ext_tags()
5499 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); in quirk_no_ext_tags()
5517 if (pdev->device == 0x15d8) { in quirk_amd_harvest_no_ats()
5518 if (pdev->revision == 0xcf && in quirk_amd_harvest_no_ats()
5519 pdev->subsystem_vendor == 0xea50 && in quirk_amd_harvest_no_ats()
5520 (pdev->subsystem_device == 0xce19 || in quirk_amd_harvest_no_ats()
5521 pdev->subsystem_device == 0xcc10 || in quirk_amd_harvest_no_ats()
5522 pdev->subsystem_device == 0xcc08)) in quirk_amd_harvest_no_ats()
5530 pdev->ats_cap = 0; in quirk_amd_harvest_no_ats()
5559 pdev->no_msi = 1; in quirk_fsl_no_msi()
5564 * Although not allowed by the spec, some multi-function devices have
5577 if (PCI_FUNC(pdev->devfn) != consumer) in pci_create_device_link()
5580 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), in pci_create_device_link()
5581 pdev->bus->number, in pci_create_device_link()
5582 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); in pci_create_device_link()
5583 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { in pci_create_device_link()
5588 if (device_link_add(&pdev->dev, &supplier_pdev->dev, in pci_create_device_link()
5596 pm_runtime_allow(&pdev->dev); in pci_create_device_link()
5629 * Create device link for GPUs with integrated Type-C UCSI controller
5656 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) in quirk_nvidia_hda()
5667 /* The GPU becomes a multi-function device when the HDA is enabled */ in quirk_nvidia_hda()
5669 gpu->multifunction = !!(hdr_type & 0x80); in quirk_nvidia_hda()
5680 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5682 * Item #36 - Downstream port applies ACS Source Validation to Completions
5695 * write, so we do config reads until we receive a non-Config Request Retry
5706 struct pci_dev *bridge = bus->self; in pci_idt_bus_quirk()
5708 pos = bridge->acs_cap; in pci_idt_bus_quirk()
5720 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ in pci_idt_bus_quirk()
5724 /* Re-enable ACS_SV if it was previously enabled */ in pci_idt_bus_quirk()
5764 partition = ioread8(&mmio_ntb->partition_id); in quirk_switchtec_ntb_dma_alias()
5766 partition_map = ioread32(&mmio_ntb->ep_map); in quirk_switchtec_ntb_dma_alias()
5767 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; in quirk_switchtec_ntb_dma_alias()
5782 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); in quirk_switchtec_ntb_dma_alias()
5799 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); in quirk_switchtec_ntb_dma_alias()
5945 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || in quirk_reset_lenovo_thinkpad_p50_nvgpu()
5946 pdev->subsystem_device != 0x222e || in quirk_reset_lenovo_thinkpad_p50_nvgpu()
5989 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); in pci_fixup_no_d0_pme()
6001 * 7.3.27, 7.3.29-7.3.31.
6007 dev->no_msi = 1; in pci_fixup_no_msi_no_pme()
6010 dev->pme_support = 0; in pci_fixup_no_msi_no_pme()
6017 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; in apex_pci_fixup_class()
6023 * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 -
6043 if (!pdev->acs_cap) in pci_fixup_pericom_acs_store_forward()
6045 pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val); in pci_fixup_pericom_acs_store_forward()
6055 pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n"); in pci_fixup_pericom_acs_store_forward()
6079 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING; in nvidia_ion_ahci_fixup()
6086 dev->rom_bar_overlap = 1; in rom_bar_overlap_defect()
6103 u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap); in aspm_l1_acceptable_latency()
6106 dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7); in aspm_l1_acceptable_latency()
6159 dev->dpc_rp_log_size = 4; in dpc_log_size()