150 	pci_read_config_dword(dev, aer + PCI_ERR_CAP, &reg32);  in enable_ecrc_checking()
174 	pci_read_config_dword(dev, aer + PCI_ERR_CAP, &reg32);  in disable_ecrc_checking()
254 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);  in pci_aer_clear_nonfatal_status()
255 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);  in pci_aer_clear_nonfatal_status()
273 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);  in pci_aer_clear_fatal_status()
274 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);  in pci_aer_clear_fatal_status()
301 		pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &status);  in pci_aer_raw_clear_status()
305 	pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);  in pci_aer_raw_clear_status()
308 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);  in pci_aer_raw_clear_status()
336 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, cap++);  in pci_save_aer_state()
337 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, cap++);  in pci_save_aer_state()
338 	pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, cap++);  in pci_save_aer_state()
339 	pci_read_config_dword(dev, aer + PCI_ERR_CAP, cap++);  in pci_save_aer_state()
341 		pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, cap++);  in pci_save_aer_state()
867 		pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);  in is_error_source()
868 		pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);  in is_error_source()
870 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);  in is_error_source()
871 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);  in is_error_source()
1063 		pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS,  in aer_get_device_error_info()
1065 		pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK,  in aer_get_device_error_info()
1075 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS,  in aer_get_device_error_info()
1077 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK,  in aer_get_device_error_info()
1083 		pci_read_config_dword(dev, aer + PCI_ERR_CAP, &temp);  in aer_get_device_error_info()
1088 			pci_read_config_dword(dev,  in aer_get_device_error_info()
1090 			pci_read_config_dword(dev,  in aer_get_device_error_info()
1092 			pci_read_config_dword(dev,  in aer_get_device_error_info()
1094 			pci_read_config_dword(dev,  in aer_get_device_error_info()
1204 	pci_read_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, &e_src.status);  in aer_irq()
1208 	pci_read_config_dword(rp, aer + PCI_ERR_ROOT_ERR_SRC, &e_src.id);  in aer_irq()
1239 	pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, &reg32);  in aer_enable_rootport()
1241 	pci_read_config_dword(pdev, aer + PCI_ERR_COR_STATUS, &reg32);  in aer_enable_rootport()
1243 	pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, &reg32);  in aer_enable_rootport()
1247 	pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_enable_rootport()
1265 	pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_disable_rootport()
1270 	pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, &reg32);  in aer_disable_rootport()
1364 		pci_read_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_root_reset()
1383 		pci_read_config_dword(root, aer + PCI_ERR_ROOT_STATUS, &reg32);  in aer_root_reset()
1387 		pci_read_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_root_reset()