Lines Matching +full:max +full:- +full:outbound +full:- +full:regions
1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
15 #include <linux/pci-epc.h>
17 #include <linux/pci-epf.h>
20 #include "pcie-rockchip.h"
23 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
26 * @max_regions: maximum number of regions supported by hardware
27 * @ob_region_map: bitmask of mapped outbound regions
28 * @ob_addr: base addresses in the AXI bus where the outbound regions start
30 * dedicated outbound regions is mapped.
35 * dedicated outbound region.
37 * the MSI/legacy IRQ dedicated outbound region.
70 int num_pass_bits = fls64(size - 1); in rockchip_pcie_prog_ep_ob_atu()
76 addr0 = ((num_pass_bits - 1) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) | in rockchip_pcie_prog_ep_ob_atu()
97 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_write_header()
101 u32 vid_regs = (hdr->vendorid & GENMASK(15, 0)) | in rockchip_pcie_ep_write_header()
102 (hdr->subsys_vendor_id & GENMASK(31, 16)) << 16; in rockchip_pcie_ep_write_header()
109 reg = (reg & 0xFFFF) | (hdr->deviceid << 16); in rockchip_pcie_ep_write_header()
113 hdr->revid | in rockchip_pcie_ep_write_header()
114 hdr->progif_code << 8 | in rockchip_pcie_ep_write_header()
115 hdr->subclass_code << 16 | in rockchip_pcie_ep_write_header()
116 hdr->baseclass_code << 24, in rockchip_pcie_ep_write_header()
118 rockchip_pcie_write(rockchip, hdr->cache_line_size, in rockchip_pcie_ep_write_header()
121 rockchip_pcie_write(rockchip, hdr->subsys_id << 16, in rockchip_pcie_ep_write_header()
124 rockchip_pcie_write(rockchip, hdr->interrupt_pin << 8, in rockchip_pcie_ep_write_header()
135 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_set_bar()
136 dma_addr_t bar_phys = epf_bar->phys_addr; in rockchip_pcie_ep_set_bar()
137 enum pci_barno bar = epf_bar->barno; in rockchip_pcie_ep_set_bar()
138 int flags = epf_bar->flags; in rockchip_pcie_ep_set_bar()
143 sz = max_t(size_t, epf_bar->size, MIN_EP_APERTURE); in rockchip_pcie_ep_set_bar()
149 sz = 1ULL << fls64(sz - 1); in rockchip_pcie_ep_set_bar()
150 aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */ in rockchip_pcie_ep_set_bar()
159 return -EINVAL; in rockchip_pcie_ep_set_bar()
178 b = bar - BAR_4; in rockchip_pcie_ep_set_bar()
203 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_clear_bar()
205 enum pci_barno bar = epf_bar->barno; in rockchip_pcie_ep_clear_bar()
212 b = bar - BAR_4; in rockchip_pcie_ep_clear_bar()
238 struct rockchip_pcie *pcie = &ep->rockchip; in rockchip_pcie_ep_map_addr()
243 set_bit(r, &ep->ob_region_map); in rockchip_pcie_ep_map_addr()
244 ep->ob_addr[r] = addr; in rockchip_pcie_ep_map_addr()
253 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_unmap_addr()
256 for (r = 0; r < ep->max_regions; r++) in rockchip_pcie_ep_unmap_addr()
257 if (ep->ob_addr[r] == addr) in rockchip_pcie_ep_unmap_addr()
260 if (r == ep->max_regions) in rockchip_pcie_ep_unmap_addr()
265 ep->ob_addr[r] = 0; in rockchip_pcie_ep_unmap_addr()
266 clear_bit(r, &ep->ob_region_map); in rockchip_pcie_ep_unmap_addr()
273 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_set_msi()
293 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_get_msi()
300 return -EINVAL; in rockchip_pcie_ep_get_msi()
309 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_assert_intx()
314 ep->irq_pending |= BIT(intx); in rockchip_pcie_ep_assert_intx()
320 ep->irq_pending &= ~BIT(intx); in rockchip_pcie_ep_assert_intx()
333 cmd = rockchip_pcie_read(&ep->rockchip, in rockchip_pcie_ep_send_legacy_irq()
338 return -EINVAL; in rockchip_pcie_ep_send_legacy_irq()
354 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_send_msi_irq()
361 flags = rockchip_pcie_read(&ep->rockchip, in rockchip_pcie_ep_send_msi_irq()
365 return -EINVAL; in rockchip_pcie_ep_send_msi_irq()
372 return -EINVAL; in rockchip_pcie_ep_send_msi_irq()
375 data_mask = msi_count - 1; in rockchip_pcie_ep_send_msi_irq()
380 data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask); in rockchip_pcie_ep_send_msi_irq()
393 /* Set the outbound region if needed. */ in rockchip_pcie_ep_send_msi_irq()
394 if (unlikely(ep->irq_pci_addr != (pci_addr & PCIE_ADDR_MASK) || in rockchip_pcie_ep_send_msi_irq()
395 ep->irq_pci_fn != fn)) { in rockchip_pcie_ep_send_msi_irq()
396 r = rockchip_ob_region(ep->irq_phys_addr); in rockchip_pcie_ep_send_msi_irq()
398 ep->irq_phys_addr, in rockchip_pcie_ep_send_msi_irq()
401 ep->irq_pci_addr = (pci_addr & PCIE_ADDR_MASK); in rockchip_pcie_ep_send_msi_irq()
402 ep->irq_pci_fn = fn; in rockchip_pcie_ep_send_msi_irq()
405 writew(data, ep->irq_cpu_addr + (pci_addr & ~PCIE_ADDR_MASK)); in rockchip_pcie_ep_send_msi_irq()
421 return -EINVAL; in rockchip_pcie_ep_raise_irq()
428 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_start()
433 list_for_each_entry(epf, &epc->pci_epf, list) in rockchip_pcie_ep_start()
434 cfg |= BIT(epf->func_no); in rockchip_pcie_ep_start()
470 struct device *dev = rockchip->dev; in rockchip_pcie_parse_ep_dt()
481 err = of_property_read_u32(dev->of_node, in rockchip_pcie_parse_ep_dt()
482 "rockchip,max-outbound-regions", in rockchip_pcie_parse_ep_dt()
483 &ep->max_regions); in rockchip_pcie_parse_ep_dt()
484 if (err < 0 || ep->max_regions > MAX_REGION_LIMIT) in rockchip_pcie_parse_ep_dt()
485 ep->max_regions = MAX_REGION_LIMIT; in rockchip_pcie_parse_ep_dt()
487 ep->ob_region_map = 0; in rockchip_pcie_parse_ep_dt()
489 err = of_property_read_u8(dev->of_node, "max-functions", in rockchip_pcie_parse_ep_dt()
490 &ep->epc->max_functions); in rockchip_pcie_parse_ep_dt()
492 ep->epc->max_functions = 1; in rockchip_pcie_parse_ep_dt()
498 { .compatible = "rockchip,rk3399-pcie-ep"},
504 struct device *dev = &pdev->dev; in rockchip_pcie_ep_probe()
515 return -ENOMEM; in rockchip_pcie_ep_probe()
517 rockchip = &ep->rockchip; in rockchip_pcie_ep_probe()
518 rockchip->is_rc = false; in rockchip_pcie_ep_probe()
519 rockchip->dev = dev; in rockchip_pcie_ep_probe()
527 ep->epc = epc; in rockchip_pcie_ep_probe()
546 max_regions = ep->max_regions; in rockchip_pcie_ep_probe()
547 ep->ob_addr = devm_kcalloc(dev, max_regions, sizeof(*ep->ob_addr), in rockchip_pcie_ep_probe()
550 if (!ep->ob_addr) { in rockchip_pcie_ep_probe()
551 err = -ENOMEM; in rockchip_pcie_ep_probe()
558 windows = devm_kcalloc(dev, ep->max_regions, in rockchip_pcie_ep_probe()
561 err = -ENOMEM; in rockchip_pcie_ep_probe()
564 for (i = 0; i < ep->max_regions; i++) { in rockchip_pcie_ep_probe()
565 windows[i].phys_base = rockchip->mem_res->start + (SZ_1M * i); in rockchip_pcie_ep_probe()
569 err = pci_epc_multi_mem_init(epc, windows, ep->max_regions); in rockchip_pcie_ep_probe()
577 ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, in rockchip_pcie_ep_probe()
579 if (!ep->irq_cpu_addr) { in rockchip_pcie_ep_probe()
581 err = -ENOMEM; in rockchip_pcie_ep_probe()
585 ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR; in rockchip_pcie_ep_probe()
588 * MSI-X is not supported but the controller still advertises the MSI-X in rockchip_pcie_ep_probe()
590 * allocating MSI-X vectors which cannot be used. Avoid this by skipping in rockchip_pcie_ep_probe()
591 * the MSI-X capability entry in the PCIe capabilities linked-list: get in rockchip_pcie_ep_probe()
592 * the next pointer from the MSI-X entry and set that in the MSI in rockchip_pcie_ep_probe()
593 * capability entry (which is the previous entry). This way the MSI-X in rockchip_pcie_ep_probe()
594 * entry is skipped (left out of the linked-list) and not advertised. in rockchip_pcie_ep_probe()
625 .name = "rockchip-pcie-ep",