Lines Matching +full:enable +full:- +full:ssc
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
26 #include <linux/pci-ecam.h>
37 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
152 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
154 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
181 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
182 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
183 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
254 bool ssc; member
273 return pcie->type == BCM7435 || pcie->type == BCM7425; in is_bmips()
278 * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
286 return (log2_in - 12) + 0x1c; in brcm_pcie_encode_ibar_size()
289 return log2_in - 15; in brcm_pcie_encode_ibar_size()
339 * Configures device for Spread Spectrum Clocking (SSC) mode; a negative
344 int pll, ssc; in brcm_pcie_set_ssc() local
348 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
353 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
366 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
371 ssc = FIELD_GET(SSC_STATUS_SSC_MASK, tmp); in brcm_pcie_set_ssc()
374 return ssc && pll ? 0 : -EIO; in brcm_pcie_set_ssc()
380 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
381 u32 lnkcap = readl(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); in brcm_pcie_set_gen()
384 writel(lnkcap, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); in brcm_pcie_set_gen()
387 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
400 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win)); in brcm_pcie_set_outbound_win()
401 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win)); in brcm_pcie_set_outbound_win()
405 limit_addr_mb = (cpu_addr + size - 1) / SZ_1M; in brcm_pcie_set_outbound_win()
407 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
412 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
422 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
425 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
428 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
431 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
457 dev = msi->dev; in brcm_pcie_msi_isr()
459 status = readl(msi->intr_base + MSI_INT_STATUS); in brcm_pcie_msi_isr()
460 status >>= msi->legacy_shift; in brcm_pcie_msi_isr()
462 for_each_set_bit(bit, &status, msi->nr) { in brcm_pcie_msi_isr()
464 ret = generic_handle_domain_irq(msi->inner_domain, bit); in brcm_pcie_msi_isr()
476 msg->address_lo = lower_32_bits(msi->target_addr); in brcm_msi_compose_msi_msg()
477 msg->address_hi = upper_32_bits(msi->target_addr); in brcm_msi_compose_msi_msg()
478 msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL_32) | data->hwirq; in brcm_msi_compose_msi_msg()
484 return -EINVAL; in brcm_msi_set_affinity()
490 const int shift_amt = data->hwirq + msi->legacy_shift; in brcm_msi_ack_irq()
492 writel(1 << shift_amt, msi->intr_base + MSI_INT_CLR); in brcm_msi_ack_irq()
507 mutex_lock(&msi->lock); in brcm_msi_alloc()
508 hwirq = bitmap_find_free_region(msi->used, msi->nr, in brcm_msi_alloc()
510 mutex_unlock(&msi->lock); in brcm_msi_alloc()
518 mutex_lock(&msi->lock); in brcm_msi_free()
519 bitmap_release_region(msi->used, hwirq, order_base_2(nr_irqs)); in brcm_msi_free()
520 mutex_unlock(&msi->lock); in brcm_msi_free()
526 struct brcm_msi *msi = domain->host_data; in brcm_irq_domain_alloc()
536 &brcm_msi_bottom_irq_chip, domain->host_data, in brcm_irq_domain_alloc()
547 brcm_msi_free(msi, d->hwirq, nr_irqs); in brcm_irq_domain_free()
557 struct fwnode_handle *fwnode = of_node_to_fwnode(msi->np); in brcm_allocate_domains()
558 struct device *dev = msi->dev; in brcm_allocate_domains()
560 msi->inner_domain = irq_domain_add_linear(NULL, msi->nr, &msi_domain_ops, msi); in brcm_allocate_domains()
561 if (!msi->inner_domain) { in brcm_allocate_domains()
563 return -ENOMEM; in brcm_allocate_domains()
566 msi->msi_domain = pci_msi_create_irq_domain(fwnode, in brcm_allocate_domains()
568 msi->inner_domain); in brcm_allocate_domains()
569 if (!msi->msi_domain) { in brcm_allocate_domains()
571 irq_domain_remove(msi->inner_domain); in brcm_allocate_domains()
572 return -ENOMEM; in brcm_allocate_domains()
580 irq_domain_remove(msi->msi_domain); in brcm_free_domains()
581 irq_domain_remove(msi->inner_domain); in brcm_free_domains()
586 struct brcm_msi *msi = pcie->msi; in brcm_msi_remove()
590 irq_set_chained_handler_and_data(msi->irq, NULL, NULL); in brcm_msi_remove()
596 u32 val = msi->legacy ? BRCM_INT_PCI_MSI_LEGACY_MASK : in brcm_msi_set_regs()
599 writel(val, msi->intr_base + MSI_INT_MASK_CLR); in brcm_msi_set_regs()
600 writel(val, msi->intr_base + MSI_INT_CLR); in brcm_msi_set_regs()
604 * enable, which we set to 1. in brcm_msi_set_regs()
606 writel(lower_32_bits(msi->target_addr) | 0x1, in brcm_msi_set_regs()
607 msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO); in brcm_msi_set_regs()
608 writel(upper_32_bits(msi->target_addr), in brcm_msi_set_regs()
609 msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI); in brcm_msi_set_regs()
611 val = msi->legacy ? PCIE_MISC_MSI_DATA_CONFIG_VAL_8 : PCIE_MISC_MSI_DATA_CONFIG_VAL_32; in brcm_msi_set_regs()
612 writel(val, msi->base + PCIE_MISC_MSI_DATA_CONFIG); in brcm_msi_set_regs()
619 struct device *dev = pcie->dev; in brcm_pcie_enable_msi()
621 irq = irq_of_parse_and_map(dev->of_node, 1); in brcm_pcie_enable_msi()
624 return -ENODEV; in brcm_pcie_enable_msi()
629 return -ENOMEM; in brcm_pcie_enable_msi()
631 mutex_init(&msi->lock); in brcm_pcie_enable_msi()
632 msi->dev = dev; in brcm_pcie_enable_msi()
633 msi->base = pcie->base; in brcm_pcie_enable_msi()
634 msi->np = pcie->np; in brcm_pcie_enable_msi()
635 msi->target_addr = pcie->msi_target_addr; in brcm_pcie_enable_msi()
636 msi->irq = irq; in brcm_pcie_enable_msi()
637 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33; in brcm_pcie_enable_msi()
645 if (msi->legacy) { in brcm_pcie_enable_msi()
646 msi->intr_base = msi->base + PCIE_INTR2_CPU_BASE; in brcm_pcie_enable_msi()
647 msi->nr = BRCM_INT_PCI_MSI_LEGACY_NR; in brcm_pcie_enable_msi()
648 msi->legacy_shift = 24; in brcm_pcie_enable_msi()
650 msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE; in brcm_pcie_enable_msi()
651 msi->nr = BRCM_INT_PCI_MSI_NR; in brcm_pcie_enable_msi()
652 msi->legacy_shift = 0; in brcm_pcie_enable_msi()
659 irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi); in brcm_pcie_enable_msi()
662 pcie->msi = msi; in brcm_pcie_enable_msi()
670 void __iomem *base = pcie->base; in brcm_pcie_rc_mode()
678 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); in brcm_pcie_link_up()
688 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_map_bus()
689 void __iomem *base = pcie->base; in brcm_pcie_map_bus()
696 /* An access to our HW w/o link-up will cause a CPU Abort */ in brcm_pcie_map_bus()
701 idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0); in brcm_pcie_map_bus()
702 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); in brcm_pcie_map_bus()
709 struct brcm_pcie *pcie = bus->sysdata; in brcm7425_pcie_map_bus()
710 void __iomem *base = pcie->base; in brcm7425_pcie_map_bus()
717 /* An access to our HW w/o link-up will cause a CPU Abort */ in brcm7425_pcie_map_bus()
722 idx = PCIE_ECAM_OFFSET(bus->number, devfn, where); in brcm7425_pcie_map_bus()
732 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
734 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
742 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
744 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
749 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n")) in brcm_pcie_perst_set_4908()
753 reset_control_assert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
755 reset_control_deassert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
763 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
765 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
772 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
774 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
783 struct device *dev = pcie->dev; in brcm_pcie_get_rc_bar2_size_and_offset()
788 resource_list_for_each_entry(entry, &bridge->dma_ranges) { in brcm_pcie_get_rc_bar2_size_and_offset()
789 u64 pcie_beg = entry->res->start - entry->offset; in brcm_pcie_get_rc_bar2_size_and_offset()
791 size += entry->res->end - entry->res->start + 1; in brcm_pcie_get_rc_bar2_size_and_offset()
797 dev_err(dev, "DT node has no dma-ranges\n"); in brcm_pcie_get_rc_bar2_size_and_offset()
798 return -EINVAL; in brcm_pcie_get_rc_bar2_size_and_offset()
801 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1, in brcm_pcie_get_rc_bar2_size_and_offset()
806 pcie->num_memc = 1; in brcm_pcie_get_rc_bar2_size_and_offset()
807 pcie->memc_size[0] = 1ULL << fls64(size - 1); in brcm_pcie_get_rc_bar2_size_and_offset()
809 pcie->num_memc = ret; in brcm_pcie_get_rc_bar2_size_and_offset()
813 for (i = 0, size = 0; i < pcie->num_memc; i++) in brcm_pcie_get_rc_bar2_size_and_offset()
814 size += pcie->memc_size[i]; in brcm_pcie_get_rc_bar2_size_and_offset()
816 /* System memory starts at this address in PCIe-space */ in brcm_pcie_get_rc_bar2_size_and_offset()
819 *rc_bar2_size = 1ULL << fls64(size - 1); in brcm_pcie_get_rc_bar2_size_and_offset()
823 * whatever the device-tree provides. This is because of an HW issue on in brcm_pcie_get_rc_bar2_size_and_offset()
825 * firmware has to dynamically edit dma-ranges due to a bug on the in brcm_pcie_get_rc_bar2_size_and_offset()
827 * lower 3GB of memory. Given this, we decided to keep the dma-ranges in brcm_pcie_get_rc_bar2_size_and_offset()
828 * in check, avoiding hard to debug device-tree related issues in the in brcm_pcie_get_rc_bar2_size_and_offset()
834 * matters, the viewport must start on a pcie-address that is aligned in brcm_pcie_get_rc_bar2_size_and_offset()
836 * represent system memory -- e.g. 3GB of memory requires a 4GB in brcm_pcie_get_rc_bar2_size_and_offset()
837 * viewport -- we can map the outbound memory in or after 3GB and even in brcm_pcie_get_rc_bar2_size_and_offset()
844 * - The best-case scenario, memory up to 3GB, is to place the inbound in brcm_pcie_get_rc_bar2_size_and_offset()
845 * region in the first 4GB of pcie-space, as some legacy devices can in brcm_pcie_get_rc_bar2_size_and_offset()
849 * - If the system memory is 4GB or larger we cannot start the inbound in brcm_pcie_get_rc_bar2_size_and_offset()
854 if (!*rc_bar2_size || (*rc_bar2_offset & (*rc_bar2_size - 1)) || in brcm_pcie_get_rc_bar2_size_and_offset()
858 return -EINVAL; in brcm_pcie_get_rc_bar2_size_and_offset()
867 void __iomem *base = pcie->base; in brcm_pcie_setup()
875 pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_setup()
878 if (pcie->type == BCM2711) in brcm_pcie_setup()
879 pcie->perst_set(pcie, 1); in brcm_pcie_setup()
884 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
902 else if (pcie->type == BCM2711) in brcm_pcie_setup()
904 else if (pcie->type == BCM7278) in brcm_pcie_setup()
934 for (memc = 0; memc < pcie->num_memc; memc++) { in brcm_pcie_setup()
935 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15; in brcm_pcie_setup()
951 * account the rounding-up we're forced to perform). in brcm_pcie_setup()
954 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB; in brcm_pcie_setup()
956 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB; in brcm_pcie_setup()
959 dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n"); in brcm_pcie_setup()
960 return -EINVAL; in brcm_pcie_setup()
963 /* disable the PCIe->GISB memory window (RC_BAR1) */ in brcm_pcie_setup()
968 /* disable the PCIe->SCB memory window (RC_BAR3) */ in brcm_pcie_setup()
973 /* Don't advertise L0s capability if 'aspm-no-l0s' */ in brcm_pcie_setup()
975 if (!of_property_read_bool(pcie->np, "aspm-no-l0s")) in brcm_pcie_setup()
984 * a PCIe-PCIe bridge (the default setting is to be EP mode). in brcm_pcie_setup()
992 resource_list_for_each_entry(entry, &bridge->windows) { in brcm_pcie_setup()
993 struct resource *res = entry->res; in brcm_pcie_setup()
999 dev_err(pcie->dev, "too many outbound wins\n"); in brcm_pcie_setup()
1000 return -EINVAL; in brcm_pcie_setup()
1004 u64 start = res->start; in brcm_pcie_setup()
1012 start - entry->offset, in brcm_pcie_setup()
1016 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start, in brcm_pcie_setup()
1017 res->start - entry->offset, in brcm_pcie_setup()
1022 /* PCIe->SCB endian mode for BAR */ in brcm_pcie_setup()
1033 struct device *dev = pcie->dev; in brcm_pcie_start_link()
1034 void __iomem *base = pcie->base; in brcm_pcie_start_link()
1041 pcie->perst_set(pcie, 0); in brcm_pcie_start_link()
1051 * configure RC. Intermittently check status for link-up, up to a in brcm_pcie_start_link()
1059 return -ENODEV; in brcm_pcie_start_link()
1062 if (pcie->gen) in brcm_pcie_start_link()
1063 brcm_pcie_set_gen(pcie, pcie->gen); in brcm_pcie_start_link()
1065 if (pcie->ssc) { in brcm_pcie_start_link()
1070 dev_err(dev, "failed attempt to enter ssc mode\n"); in brcm_pcie_start_link()
1078 ssc_good ? "(SSC)" : "(!SSC)"); in brcm_pcie_start_link()
1106 sr->num_supplies = ARRAY_SIZE(supplies); in alloc_subdev_regulators()
1108 sr->supplies[i].supply = supplies[i]; in alloc_subdev_regulators()
1116 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_add_bus()
1117 struct device *dev = &bus->dev; in brcm_pcie_add_bus()
1121 if (!bus->parent || !pci_is_root_bus(bus->parent)) in brcm_pcie_add_bus()
1124 if (dev->of_node) { in brcm_pcie_add_bus()
1131 pcie->sr = sr; in brcm_pcie_add_bus()
1133 ret = regulator_bulk_get(dev, sr->num_supplies, sr->supplies); in brcm_pcie_add_bus()
1139 ret = regulator_bulk_enable(sr->num_supplies, sr->supplies); in brcm_pcie_add_bus()
1141 dev_err(dev, "Can't enable regulators for downstream device\n"); in brcm_pcie_add_bus()
1142 regulator_bulk_free(sr->num_supplies, sr->supplies); in brcm_pcie_add_bus()
1143 pcie->sr = NULL; in brcm_pcie_add_bus()
1154 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_remove_bus()
1155 struct subdev_regulators *sr = pcie->sr; in brcm_pcie_remove_bus()
1156 struct device *dev = &bus->dev; in brcm_pcie_remove_bus()
1161 if (regulator_bulk_disable(sr->num_supplies, sr->supplies)) in brcm_pcie_remove_bus()
1163 regulator_bulk_free(sr->num_supplies, sr->supplies); in brcm_pcie_remove_bus()
1164 pcie->sr = NULL; in brcm_pcie_remove_bus()
1167 /* L23 is a low-power PCIe link state */
1170 void __iomem *base = pcie->base; in brcm_pcie_enter_l23()
1190 dev_err(pcie->dev, "failed to enter low-power link state\n"); in brcm_pcie_enter_l23()
1203 const int beg = start ? 0 : PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS - 1; in brcm_phy_cntl()
1204 const int end = start ? PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS : -1; in brcm_phy_cntl()
1207 void __iomem *base = pcie->base; in brcm_phy_cntl()
1210 for (i = beg; i != end; start ? i++ : i--) { in brcm_phy_cntl()
1222 ret = (tmp & combined_mask) == val ? 0 : -EIO; in brcm_phy_cntl()
1224 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop")); in brcm_phy_cntl()
1231 return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0; in brcm_phy_start()
1236 return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0; in brcm_phy_stop()
1241 void __iomem *base = pcie->base; in brcm_pcie_turn_off()
1247 pcie->perst_set(pcie, 1); in brcm_pcie_turn_off()
1260 pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_turn_off()
1267 if (device_may_wakeup(&dev->dev)) { in pci_dev_may_wakeup()
1269 dev_info(&dev->dev, "Possible wake-up device; regulators will not be disabled\n"); in pci_dev_may_wakeup()
1289 ret = reset_control_rearm(pcie->rescal); in brcm_pcie_suspend_noirq()
1295 if (pcie->sr) { in brcm_pcie_suspend_noirq()
1298 * downstream device is enabled as a wake-up source, do not in brcm_pcie_suspend_noirq()
1301 pcie->ep_wakeup_capable = false; in brcm_pcie_suspend_noirq()
1302 pci_walk_bus(bridge->bus, pci_dev_may_wakeup, in brcm_pcie_suspend_noirq()
1303 &pcie->ep_wakeup_capable); in brcm_pcie_suspend_noirq()
1304 if (!pcie->ep_wakeup_capable) { in brcm_pcie_suspend_noirq()
1305 ret = regulator_bulk_disable(pcie->sr->num_supplies, in brcm_pcie_suspend_noirq()
1306 pcie->sr->supplies); in brcm_pcie_suspend_noirq()
1309 reset_control_reset(pcie->rescal); in brcm_pcie_suspend_noirq()
1314 clk_disable_unprepare(pcie->clk); in brcm_pcie_suspend_noirq()
1326 base = pcie->base; in brcm_pcie_resume_noirq()
1327 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_resume_noirq()
1331 ret = reset_control_reset(pcie->rescal); in brcm_pcie_resume_noirq()
1340 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_resume_noirq()
1354 if (pcie->sr) { in brcm_pcie_resume_noirq()
1355 if (pcie->ep_wakeup_capable) { in brcm_pcie_resume_noirq()
1359 * no need to enable them (and falsely increase their in brcm_pcie_resume_noirq()
1362 pcie->ep_wakeup_capable = false; in brcm_pcie_resume_noirq()
1364 ret = regulator_bulk_enable(pcie->sr->num_supplies, in brcm_pcie_resume_noirq()
1365 pcie->sr->supplies); in brcm_pcie_resume_noirq()
1377 if (pcie->msi) in brcm_pcie_resume_noirq()
1378 brcm_msi_set_regs(pcie->msi); in brcm_pcie_resume_noirq()
1383 if (pcie->sr) in brcm_pcie_resume_noirq()
1384 regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies); in brcm_pcie_resume_noirq()
1386 reset_control_rearm(pcie->rescal); in brcm_pcie_resume_noirq()
1388 clk_disable_unprepare(pcie->clk); in brcm_pcie_resume_noirq()
1397 dev_err(pcie->dev, "Could not stop phy\n"); in __brcm_pcie_remove()
1398 if (reset_control_rearm(pcie->rescal)) in __brcm_pcie_remove()
1399 dev_err(pcie->dev, "Could not rearm rescal reset\n"); in __brcm_pcie_remove()
1400 clk_disable_unprepare(pcie->clk); in __brcm_pcie_remove()
1408 pci_stop_root_bus(bridge->bus); in brcm_pcie_remove()
1409 pci_remove_root_bus(bridge->bus); in brcm_pcie_remove()
1474 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1475 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
1476 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1477 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1478 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
1479 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1480 { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
1481 { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
1503 struct device_node *np = pdev->dev.of_node, *msi_np; in brcm_pcie_probe()
1509 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie)); in brcm_pcie_probe()
1511 return -ENOMEM; in brcm_pcie_probe()
1513 data = of_device_get_match_data(&pdev->dev); in brcm_pcie_probe()
1516 return -EINVAL; in brcm_pcie_probe()
1520 pcie->dev = &pdev->dev; in brcm_pcie_probe()
1521 pcie->np = np; in brcm_pcie_probe()
1522 pcie->reg_offsets = data->offsets; in brcm_pcie_probe()
1523 pcie->type = data->type; in brcm_pcie_probe()
1524 pcie->perst_set = data->perst_set; in brcm_pcie_probe()
1525 pcie->bridge_sw_init_set = data->bridge_sw_init_set; in brcm_pcie_probe()
1527 pcie->base = devm_platform_ioremap_resource(pdev, 0); in brcm_pcie_probe()
1528 if (IS_ERR(pcie->base)) in brcm_pcie_probe()
1529 return PTR_ERR(pcie->base); in brcm_pcie_probe()
1531 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie"); in brcm_pcie_probe()
1532 if (IS_ERR(pcie->clk)) in brcm_pcie_probe()
1533 return PTR_ERR(pcie->clk); in brcm_pcie_probe()
1536 pcie->gen = (ret < 0) ? 0 : ret; in brcm_pcie_probe()
1538 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); in brcm_pcie_probe()
1540 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_probe()
1542 dev_err(&pdev->dev, "could not enable clock\n"); in brcm_pcie_probe()
1545 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal"); in brcm_pcie_probe()
1546 if (IS_ERR(pcie->rescal)) { in brcm_pcie_probe()
1547 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1548 return PTR_ERR(pcie->rescal); in brcm_pcie_probe()
1550 pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst"); in brcm_pcie_probe()
1551 if (IS_ERR(pcie->perst_reset)) { in brcm_pcie_probe()
1552 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1553 return PTR_ERR(pcie->perst_reset); in brcm_pcie_probe()
1556 ret = reset_control_reset(pcie->rescal); in brcm_pcie_probe()
1558 dev_err(&pdev->dev, "failed to deassert 'rescal'\n"); in brcm_pcie_probe()
1562 reset_control_rearm(pcie->rescal); in brcm_pcie_probe()
1563 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1571 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION); in brcm_pcie_probe()
1572 if (pcie->type == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) { in brcm_pcie_probe()
1573 dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n"); in brcm_pcie_probe()
1574 ret = -ENODEV; in brcm_pcie_probe()
1578 msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); in brcm_pcie_probe()
1579 if (pci_msi_enabled() && msi_np == pcie->np) { in brcm_pcie_probe()
1582 dev_err(pcie->dev, "probe of internal MSI failed"); in brcm_pcie_probe()
1587 bridge->ops = pcie->type == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops; in brcm_pcie_probe()
1588 bridge->sysdata = pcie; in brcm_pcie_probe()
1594 ret = -ENODEV; in brcm_pcie_probe()
1619 .name = "brcm-pcie",