Lines Matching +full:ecam +full:- +full:based
1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/pci-ecam.h>
30 #include "../pci-bridge-emul.h"
140 #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
295 writel(val, pcie->base + reg); in advk_writel()
300 return readl(pcie->base + reg); in advk_readl()
315 /* check if LTSSM is in normal operation - some L* state */ in advk_pcie_link_up()
323 * According to PCIe Base specification 3.0, Table 4-14: Link in advk_pcie_link_active()
337 * According to PCIe Base specification 3.0, Table 4-14: Link in advk_pcie_link_training()
360 return -ETIMEDOUT; in advk_pcie_wait_for_link()
376 if (!pcie->reset_gpio) in advk_pcie_issue_perst()
380 dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n"); in advk_pcie_issue_perst()
381 gpiod_set_value_cansleep(pcie->reset_gpio, 1); in advk_pcie_issue_perst()
383 gpiod_set_value_cansleep(pcie->reset_gpio, 0); in advk_pcie_issue_perst()
388 struct device *dev = &pcie->pdev->dev; in advk_pcie_train_link()
393 * Setup PCIe rev / gen compliance based on device tree property in advk_pcie_train_link()
394 * 'max-link-speed' which also forces maximal link speed. in advk_pcie_train_link()
398 if (pcie->link_gen == 3) in advk_pcie_train_link()
400 else if (pcie->link_gen == 2) in advk_pcie_train_link()
408 * Armada 3700 Functional Specification says that default value is based in advk_pcie_train_link()
413 if (pcie->link_gen == 3) in advk_pcie_train_link()
415 else if (pcie->link_gen == 2) in advk_pcie_train_link()
428 * during link training when they are in some non-initial state. in advk_pcie_train_link()
488 * Reference clock differential signal off-chip and disable in advk_pcie_setup_hw()
489 * receiving off-chip differential signal. in advk_pcie_setup_hw()
511 * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround in advk_pcie_setup_hw()
525 * and is reported as Type 0. In range 0x10 - 0x34 it has totally in advk_pcie_setup_hw()
637 * Configure PCIe address windows for non-memory or in advk_pcie_setup_hw()
638 * non-transparent access as by default PCIe uses in advk_pcie_setup_hw()
641 for (i = 0; i < pcie->wins_count; i++) in advk_pcie_setup_hw()
643 pcie->wins[i].match, pcie->wins[i].remap, in advk_pcie_setup_hw()
644 pcie->wins[i].mask, pcie->wins[i].actions); in advk_pcie_setup_hw()
647 for (i = pcie->wins_count; i < OB_WIN_COUNT; i++) in advk_pcie_setup_hw()
655 struct device *dev = &pcie->pdev->dev; in advk_pcie_check_pio_status()
684 ret = -EFAULT; in advk_pcie_check_pio_status()
696 ret = -EOPNOTSUPP; in advk_pcie_check_pio_status()
706 * read-data value of 0001h for the Vendor ID field and in advk_pcie_check_pio_status()
719 * must re-issue the Configuration Request as a new Request. in advk_pcie_check_pio_status()
722 * the Root Complex must re-issue the Configuration Request as in advk_pcie_check_pio_status()
730 * So return -EAGAIN and caller (pci-aardvark.c driver) will in advk_pcie_check_pio_status()
731 * re-issue request again up to the PIO_RETRY_CNT retries. in advk_pcie_check_pio_status()
734 ret = -EAGAIN; in advk_pcie_check_pio_status()
738 ret = -ECANCELED; in advk_pcie_check_pio_status()
742 ret = -EINVAL; in advk_pcie_check_pio_status()
750 str_posted = "Non-posted"; in advk_pcie_check_pio_status()
762 struct device *dev = &pcie->pdev->dev; in advk_pcie_wait_pio()
776 return -ETIMEDOUT; in advk_pcie_wait_pio()
783 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_base_conf_read()
796 __le32 *cfgspace = (__le32 *)&bridge->conf; in advk_pci_bridge_emul_base_conf_read()
819 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_base_conf_write()
828 * According to Figure 6-3: Pseudo Logic Diagram for Error in advk_pci_bridge_emul_base_conf_write()
859 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_pcie_conf_read()
913 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_pcie_conf_write()
923 u16 rootctl = le16_to_cpu(bridge->pcie_conf.rootctl); in advk_pci_bridge_emul_pcie_conf_write()
926 bridge->pcie_conf.rootctl = cpu_to_le16(rootctl); in advk_pci_bridge_emul_pcie_conf_write()
951 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_ext_conf_read()
995 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_ext_conf_write()
1033 * Initialize the configuration space of the PCI-to-PCI bridge
1038 struct pci_bridge_emul *bridge = &pcie->bridge; in advk_sw_pci_bridge_init()
1040 bridge->conf.vendor = in advk_sw_pci_bridge_init()
1042 bridge->conf.device = in advk_sw_pci_bridge_init()
1044 bridge->conf.class_revision = in advk_sw_pci_bridge_init()
1048 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32; in advk_sw_pci_bridge_init()
1049 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32; in advk_sw_pci_bridge_init()
1052 bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); in advk_sw_pci_bridge_init()
1053 bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); in advk_sw_pci_bridge_init()
1056 bridge->conf.intpin = PCI_INTERRUPT_INTA; in advk_sw_pci_bridge_init()
1062 bridge->pcie_conf.cap = cpu_to_le16(2 | PCI_EXP_FLAGS_SLOT); in advk_sw_pci_bridge_init()
1074 bridge->pcie_conf.slotcap = cpu_to_le32(FIELD_PREP(PCI_EXP_SLTCAP_PSN, in advk_sw_pci_bridge_init()
1076 bridge->pcie_conf.slotsta = cpu_to_le16(PCI_EXP_SLTSTA_PDS); in advk_sw_pci_bridge_init()
1079 bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_CRSVIS); in advk_sw_pci_bridge_init()
1081 bridge->subsystem_vendor_id = advk_readl(pcie, PCIE_CORE_SSDEV_ID_REG) & 0xffff; in advk_sw_pci_bridge_init()
1082 bridge->subsystem_id = advk_readl(pcie, PCIE_CORE_SSDEV_ID_REG) >> 16; in advk_sw_pci_bridge_init()
1083 bridge->has_pcie = true; in advk_sw_pci_bridge_init()
1084 bridge->pcie_start = PCIE_CORE_PCIEXP_CAP; in advk_sw_pci_bridge_init()
1085 bridge->data = pcie; in advk_sw_pci_bridge_init()
1086 bridge->ops = &advk_pci_bridge_emul_ops; in advk_sw_pci_bridge_init()
1098 * If the link goes down after we check for link-up, we have a problem: in advk_pcie_valid_device()
1099 * if a PIO request is executed while link-down, the whole controller in advk_pcie_valid_device()
1100 * gets stuck in a non-functional state, and even after link comes up in advk_pcie_valid_device()
1113 struct device *dev = &pcie->pdev->dev; in advk_pcie_pio_is_running()
1119 * SError Interrupt on CPU0, code 0xbf000002 -- SError in advk_pcie_pio_is_running()
1120 * Kernel panic - not syncing: Asynchronous SError Interrupt in advk_pcie_pio_is_running()
1129 * EL3 level and mask it to prevent kernel panic. Relevant TF-A commit: in advk_pcie_pio_is_running()
1130 * https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50 in advk_pcie_pio_is_running()
1143 struct advk_pcie *pcie = bus->sysdata; in advk_pcie_rd_conf()
1153 return pci_bridge_emul_conf_read(&pcie->bridge, where, in advk_pcie_rd_conf()
1162 (le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & in advk_pcie_rd_conf()
1171 if (pci_is_root_bus(bus->parent)) in advk_pcie_rd_conf()
1178 reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); in advk_pcie_rd_conf()
1199 } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT); in advk_pcie_rd_conf()
1229 struct advk_pcie *pcie = bus->sysdata; in advk_pcie_wr_conf()
1240 return pci_bridge_emul_conf_write(&pcie->bridge, where, in advk_pcie_wr_conf()
1252 if (pci_is_root_bus(bus->parent)) in advk_pcie_wr_conf()
1259 reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); in advk_pcie_wr_conf()
1266 data_strobe = GENMASK(size - 1, 0) << offset; in advk_pcie_wr_conf()
1287 } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT); in advk_pcie_wr_conf()
1303 msg->address_lo = lower_32_bits(msi_addr); in advk_msi_irq_compose_msi_msg()
1304 msg->address_hi = upper_32_bits(msi_addr); in advk_msi_irq_compose_msi_msg()
1305 msg->data = data->hwirq; in advk_msi_irq_compose_msi_msg()
1311 return -EINVAL; in advk_msi_set_affinity()
1316 struct advk_pcie *pcie = d->domain->host_data; in advk_msi_irq_mask()
1321 raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags); in advk_msi_irq_mask()
1325 raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags); in advk_msi_irq_mask()
1330 struct advk_pcie *pcie = d->domain->host_data; in advk_msi_irq_unmask()
1335 raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags); in advk_msi_irq_unmask()
1339 raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags); in advk_msi_irq_unmask()
1366 struct advk_pcie *pcie = domain->host_data; in advk_msi_irq_domain_alloc()
1369 mutex_lock(&pcie->msi_used_lock); in advk_msi_irq_domain_alloc()
1370 hwirq = bitmap_find_free_region(pcie->msi_used, MSI_IRQ_NUM, in advk_msi_irq_domain_alloc()
1372 mutex_unlock(&pcie->msi_used_lock); in advk_msi_irq_domain_alloc()
1374 return -ENOSPC; in advk_msi_irq_domain_alloc()
1379 domain->host_data, handle_simple_irq, in advk_msi_irq_domain_alloc()
1389 struct advk_pcie *pcie = domain->host_data; in advk_msi_irq_domain_free()
1391 mutex_lock(&pcie->msi_used_lock); in advk_msi_irq_domain_free()
1392 bitmap_release_region(pcie->msi_used, d->hwirq, order_base_2(nr_irqs)); in advk_msi_irq_domain_free()
1393 mutex_unlock(&pcie->msi_used_lock); in advk_msi_irq_domain_free()
1403 struct advk_pcie *pcie = d->domain->host_data; in advk_pcie_irq_mask()
1408 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in advk_pcie_irq_mask()
1412 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in advk_pcie_irq_mask()
1417 struct advk_pcie *pcie = d->domain->host_data; in advk_pcie_irq_unmask()
1422 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in advk_pcie_irq_unmask()
1426 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in advk_pcie_irq_unmask()
1432 struct advk_pcie *pcie = h->host_data; in advk_pcie_irq_map()
1435 irq_set_chip_and_handler(virq, &pcie->irq_chip, in advk_pcie_irq_map()
1448 .name = "advk-MSI",
1461 struct device *dev = &pcie->pdev->dev; in advk_pcie_init_msi_irq_domain()
1463 raw_spin_lock_init(&pcie->msi_irq_lock); in advk_pcie_init_msi_irq_domain()
1464 mutex_init(&pcie->msi_used_lock); in advk_pcie_init_msi_irq_domain()
1466 pcie->msi_inner_domain = in advk_pcie_init_msi_irq_domain()
1469 if (!pcie->msi_inner_domain) in advk_pcie_init_msi_irq_domain()
1470 return -ENOMEM; in advk_pcie_init_msi_irq_domain()
1472 pcie->msi_domain = in advk_pcie_init_msi_irq_domain()
1475 pcie->msi_inner_domain); in advk_pcie_init_msi_irq_domain()
1476 if (!pcie->msi_domain) { in advk_pcie_init_msi_irq_domain()
1477 irq_domain_remove(pcie->msi_inner_domain); in advk_pcie_init_msi_irq_domain()
1478 return -ENOMEM; in advk_pcie_init_msi_irq_domain()
1486 irq_domain_remove(pcie->msi_domain); in advk_pcie_remove_msi_irq_domain()
1487 irq_domain_remove(pcie->msi_inner_domain); in advk_pcie_remove_msi_irq_domain()
1492 struct device *dev = &pcie->pdev->dev; in advk_pcie_init_irq_domain()
1493 struct device_node *node = dev->of_node; in advk_pcie_init_irq_domain()
1498 raw_spin_lock_init(&pcie->irq_lock); in advk_pcie_init_irq_domain()
1503 return -ENODEV; in advk_pcie_init_irq_domain()
1506 irq_chip = &pcie->irq_chip; in advk_pcie_init_irq_domain()
1508 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq", in advk_pcie_init_irq_domain()
1510 if (!irq_chip->name) { in advk_pcie_init_irq_domain()
1511 ret = -ENOMEM; in advk_pcie_init_irq_domain()
1515 irq_chip->irq_mask = advk_pcie_irq_mask; in advk_pcie_init_irq_domain()
1516 irq_chip->irq_unmask = advk_pcie_irq_unmask; in advk_pcie_init_irq_domain()
1518 pcie->irq_domain = in advk_pcie_init_irq_domain()
1521 if (!pcie->irq_domain) { in advk_pcie_init_irq_domain()
1523 ret = -ENOMEM; in advk_pcie_init_irq_domain()
1534 irq_domain_remove(pcie->irq_domain); in advk_pcie_remove_irq_domain()
1538 .name = "advk-RP",
1544 struct advk_pcie *pcie = h->host_data; in advk_pcie_rp_irq_map()
1559 pcie->rp_irq_domain = irq_domain_add_linear(NULL, 1, in advk_pcie_init_rp_irq_domain()
1562 if (!pcie->rp_irq_domain) { in advk_pcie_init_rp_irq_domain()
1563 dev_err(&pcie->pdev->dev, "Failed to add Root Port IRQ domain\n"); in advk_pcie_init_rp_irq_domain()
1564 return -ENOMEM; in advk_pcie_init_rp_irq_domain()
1572 irq_domain_remove(pcie->rp_irq_domain); in advk_pcie_remove_rp_irq_domain()
1586 if (!(le32_to_cpu(pcie->bridge.pcie_conf.rootsta) & PCI_EXP_RTSTA_PME)) { in advk_pcie_handle_pme()
1587 pcie->bridge.pcie_conf.rootsta = cpu_to_le32(requester | PCI_EXP_RTSTA_PME); in advk_pcie_handle_pme()
1593 if (!(le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & PCI_EXP_RTCTL_PMEIE)) in advk_pcie_handle_pme()
1596 if (generic_handle_domain_irq(pcie->rp_irq_domain, 0) == -EINVAL) in advk_pcie_handle_pme()
1597 dev_err_ratelimited(&pcie->pdev->dev, "unhandled PME IRQ\n"); in advk_pcie_handle_pme()
1614 if (generic_handle_domain_irq(pcie->msi_inner_domain, msi_idx) == -EINVAL) in advk_pcie_handle_msi()
1615 dev_err_ratelimited(&pcie->pdev->dev, "unexpected MSI 0x%02x\n", msi_idx); in advk_pcie_handle_msi()
1648 if (generic_handle_domain_irq(pcie->rp_irq_domain, 0) == -EINVAL) in advk_pcie_handle_int()
1649 dev_err_ratelimited(&pcie->pdev->dev, "unhandled ERR IRQ\n"); in advk_pcie_handle_int()
1664 if (generic_handle_domain_irq(pcie->irq_domain, i) == -EINVAL) in advk_pcie_handle_int()
1665 dev_err_ratelimited(&pcie->pdev->dev, "unexpected INT%c IRQ\n", in advk_pcie_handle_int()
1689 struct advk_pcie *pcie = dev->bus->sysdata; in advk_pcie_map_irq()
1696 if (pci_is_root_bus(dev->bus)) in advk_pcie_map_irq()
1697 return irq_create_mapping(pcie->rp_irq_domain, pin - 1); in advk_pcie_map_irq()
1704 phy_power_off(pcie->phy); in advk_pcie_disable_phy()
1705 phy_exit(pcie->phy); in advk_pcie_disable_phy()
1712 if (!pcie->phy) in advk_pcie_enable_phy()
1715 ret = phy_init(pcie->phy); in advk_pcie_enable_phy()
1719 ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE); in advk_pcie_enable_phy()
1721 phy_exit(pcie->phy); in advk_pcie_enable_phy()
1725 ret = phy_power_on(pcie->phy); in advk_pcie_enable_phy()
1727 phy_exit(pcie->phy); in advk_pcie_enable_phy()
1736 struct device *dev = &pcie->pdev->dev; in advk_pcie_setup_phy()
1737 struct device_node *node = dev->of_node; in advk_pcie_setup_phy()
1740 pcie->phy = devm_of_phy_get(dev, node, NULL); in advk_pcie_setup_phy()
1741 if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER)) in advk_pcie_setup_phy()
1742 return PTR_ERR(pcie->phy); in advk_pcie_setup_phy()
1745 if (IS_ERR(pcie->phy)) { in advk_pcie_setup_phy()
1746 dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy)); in advk_pcie_setup_phy()
1747 pcie->phy = NULL; in advk_pcie_setup_phy()
1760 struct device *dev = &pdev->dev; in advk_pcie_probe()
1768 return -ENOMEM; in advk_pcie_probe()
1771 pcie->pdev = pdev; in advk_pcie_probe()
1774 resource_list_for_each_entry(entry, &bridge->windows) { in advk_pcie_probe()
1775 resource_size_t start = entry->res->start; in advk_pcie_probe()
1776 resource_size_t size = resource_size(entry->res); in advk_pcie_probe()
1777 unsigned long type = resource_type(entry->res); in advk_pcie_probe()
1794 if (type == IORESOURCE_MEM && entry->offset == 0) in advk_pcie_probe()
1798 * The n-th PCIe window is configured by tuple (match, remap, mask) in advk_pcie_probe()
1806 while (pcie->wins_count < OB_WIN_COUNT && size > 0) { in advk_pcie_probe()
1808 win_size = (1ULL << (fls64(size)-1)) | in advk_pcie_probe()
1815 "Configuring PCIe window %d: [0x%llx-0x%llx] as %lu\n", in advk_pcie_probe()
1816 pcie->wins_count, (unsigned long long)start, in advk_pcie_probe()
1820 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_IO; in advk_pcie_probe()
1821 pcie->wins[pcie->wins_count].match = pci_pio_to_address(start); in advk_pcie_probe()
1823 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_MEM; in advk_pcie_probe()
1824 pcie->wins[pcie->wins_count].match = start; in advk_pcie_probe()
1826 pcie->wins[pcie->wins_count].remap = start - entry->offset; in advk_pcie_probe()
1827 pcie->wins[pcie->wins_count].mask = ~(win_size - 1); in advk_pcie_probe()
1829 if (pcie->wins[pcie->wins_count].remap & (win_size - 1)) in advk_pcie_probe()
1833 size -= win_size; in advk_pcie_probe()
1834 pcie->wins_count++; in advk_pcie_probe()
1838 dev_err(&pcie->pdev->dev, in advk_pcie_probe()
1839 "Invalid PCIe region [0x%llx-0x%llx]\n", in advk_pcie_probe()
1840 (unsigned long long)entry->res->start, in advk_pcie_probe()
1841 (unsigned long long)entry->res->end + 1); in advk_pcie_probe()
1842 return -EINVAL; in advk_pcie_probe()
1846 pcie->base = devm_platform_ioremap_resource(pdev, 0); in advk_pcie_probe()
1847 if (IS_ERR(pcie->base)) in advk_pcie_probe()
1848 return PTR_ERR(pcie->base); in advk_pcie_probe()
1855 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie", in advk_pcie_probe()
1862 pcie->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); in advk_pcie_probe()
1863 ret = PTR_ERR_OR_ZERO(pcie->reset_gpio); in advk_pcie_probe()
1865 if (ret != -EPROBE_DEFER) in advk_pcie_probe()
1866 dev_err(dev, "Failed to get reset-gpio: %i\n", ret); in advk_pcie_probe()
1870 ret = gpiod_set_consumer_name(pcie->reset_gpio, "pcie1-reset"); in advk_pcie_probe()
1876 ret = of_pci_get_max_link_speed(dev->of_node); in advk_pcie_probe()
1878 pcie->link_gen = 3; in advk_pcie_probe()
1880 pcie->link_gen = ret; in advk_pcie_probe()
1915 bridge->sysdata = pcie; in advk_pcie_probe()
1916 bridge->ops = &advk_pcie_ops; in advk_pcie_probe()
1917 bridge->map_irq = advk_pcie_map_irq; in advk_pcie_probe()
1939 pci_stop_root_bus(bridge->bus); in advk_pcie_remove()
1940 pci_remove_root_bus(bridge->bus); in advk_pcie_remove()
1975 pci_bridge_emul_cleanup(&pcie->bridge); in advk_pcie_remove()
1978 if (pcie->reset_gpio) in advk_pcie_remove()
1979 gpiod_set_value_cansleep(pcie->reset_gpio, 1); in advk_pcie_remove()
1995 { .compatible = "marvell,armada-3700-pcie", },
2002 .name = "advk-pcie",