49 #define APPL_CTRL				0x4  macro
468 	val = appl_readl(pcie, APPL_CTRL);  in pex_ep_event_hot_rst_done()
470 	appl_writel(pcie, val, APPL_CTRL);  in pex_ep_event_hot_rst_done()
983 	val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_dw_start_link()
985 	appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_dw_start_link()
1018 		val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_dw_start_link()
1020 		appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_dw_start_link()
1426 		val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_config_controller()
1432 		appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_config_controller()
1450 	val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_config_controller()
1451 	appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL);  in tegra_pcie_config_controller()
1614 		data = readl(pcie->appl_base + APPL_CTRL);  in tegra_pcie_dw_pme_turnoff()
1616 		writel(data, pcie->appl_base + APPL_CTRL);  in tegra_pcie_dw_pme_turnoff()
1709 	val = appl_readl(pcie, APPL_CTRL);  in pex_ep_event_pex_rst_assert()
1711 	appl_writel(pcie, val, APPL_CTRL);  in pex_ep_event_pex_rst_assert()
1824 	val = appl_readl(pcie, APPL_CTRL);  in pex_ep_event_pex_rst_deassert()
1827 	appl_writel(pcie, val, APPL_CTRL);  in pex_ep_event_pex_rst_deassert()
1917 	val = appl_readl(pcie, APPL_CTRL);  in pex_ep_event_pex_rst_deassert()
1919 	appl_writel(pcie, val, APPL_CTRL);  in pex_ep_event_pex_rst_deassert()
2325 		val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_dw_suspend_late()
2329 		appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_dw_suspend_late()
2395 		val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_dw_resume_early()
2401 		appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_dw_resume_early()