Lines Matching +full:max +full:- +full:outbound +full:- +full:regions
1 // SPDX-License-Identifier: GPL-2.0
24 #include "pcie-designware.h"
46 [DW_PCIE_NON_STICKY_RST] = "non-sticky",
60 pci->app_clks[i].id = dw_pcie_app_clks[i]; in dw_pcie_get_clocks()
63 pci->core_clks[i].id = dw_pcie_core_clks[i]; in dw_pcie_get_clocks()
65 ret = devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_APP_CLKS, in dw_pcie_get_clocks()
66 pci->app_clks); in dw_pcie_get_clocks()
70 return devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_CORE_CLKS, in dw_pcie_get_clocks()
71 pci->core_clks); in dw_pcie_get_clocks()
79 pci->app_rsts[i].id = dw_pcie_app_rsts[i]; in dw_pcie_get_resets()
82 pci->core_rsts[i].id = dw_pcie_core_rsts[i]; in dw_pcie_get_resets()
84 ret = devm_reset_control_bulk_get_optional_shared(pci->dev, in dw_pcie_get_resets()
86 pci->app_rsts); in dw_pcie_get_resets()
90 ret = devm_reset_control_bulk_get_optional_exclusive(pci->dev, in dw_pcie_get_resets()
92 pci->core_rsts); in dw_pcie_get_resets()
96 pci->pe_rst = devm_gpiod_get_optional(pci->dev, "reset", GPIOD_OUT_HIGH); in dw_pcie_get_resets()
97 if (IS_ERR(pci->pe_rst)) in dw_pcie_get_resets()
98 return PTR_ERR(pci->pe_rst); in dw_pcie_get_resets()
105 struct platform_device *pdev = to_platform_device(pci->dev); in dw_pcie_get_resources()
106 struct device_node *np = dev_of_node(pci->dev); in dw_pcie_get_resources()
110 if (!pci->dbi_base) { in dw_pcie_get_resources()
112 pci->dbi_base = devm_pci_remap_cfg_resource(pci->dev, res); in dw_pcie_get_resources()
113 if (IS_ERR(pci->dbi_base)) in dw_pcie_get_resources()
114 return PTR_ERR(pci->dbi_base); in dw_pcie_get_resources()
118 if (!pci->dbi_base2) { in dw_pcie_get_resources()
121 pci->dbi_base2 = devm_pci_remap_cfg_resource(pci->dev, res); in dw_pcie_get_resources()
122 if (IS_ERR(pci->dbi_base2)) in dw_pcie_get_resources()
123 return PTR_ERR(pci->dbi_base2); in dw_pcie_get_resources()
125 pci->dbi_base2 = pci->dbi_base + SZ_4K; in dw_pcie_get_resources()
129 /* For non-unrolled iATU/eDMA platforms this range will be ignored */ in dw_pcie_get_resources()
130 if (!pci->atu_base) { in dw_pcie_get_resources()
133 pci->atu_size = resource_size(res); in dw_pcie_get_resources()
134 pci->atu_base = devm_ioremap_resource(pci->dev, res); in dw_pcie_get_resources()
135 if (IS_ERR(pci->atu_base)) in dw_pcie_get_resources()
136 return PTR_ERR(pci->atu_base); in dw_pcie_get_resources()
138 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; in dw_pcie_get_resources()
143 if (!pci->atu_size) in dw_pcie_get_resources()
144 pci->atu_size = SZ_4K; in dw_pcie_get_resources()
147 if (!pci->edma.reg_base) { in dw_pcie_get_resources()
150 pci->edma.reg_base = devm_ioremap_resource(pci->dev, res); in dw_pcie_get_resources()
151 if (IS_ERR(pci->edma.reg_base)) in dw_pcie_get_resources()
152 return PTR_ERR(pci->edma.reg_base); in dw_pcie_get_resources()
153 } else if (pci->atu_size >= 2 * DEFAULT_DBI_DMA_OFFSET) { in dw_pcie_get_resources()
154 pci->edma.reg_base = pci->atu_base + DEFAULT_DBI_DMA_OFFSET; in dw_pcie_get_resources()
169 if (pci->link_gen < 1) in dw_pcie_get_resources()
170 pci->link_gen = of_pci_get_max_link_speed(np); in dw_pcie_get_resources()
172 of_property_read_u32(np, "num-lanes", &pci->num_lanes); in dw_pcie_get_resources()
174 if (of_property_read_bool(np, "snps,enable-cdm-check")) in dw_pcie_get_resources()
189 if (pci->version && pci->version != ver) in dw_pcie_version_detect()
190 dev_warn(pci->dev, "Versions don't match (%08x != %08x)\n", in dw_pcie_version_detect()
191 pci->version, ver); in dw_pcie_version_detect()
193 pci->version = ver; in dw_pcie_version_detect()
197 if (pci->type && pci->type != ver) in dw_pcie_version_detect()
198 dev_warn(pci->dev, "Types don't match (%08x != %08x)\n", in dw_pcie_version_detect()
199 pci->type, ver); in dw_pcie_version_detect()
201 pci->type = ver; in dw_pcie_version_detect()
251 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; in dw_pcie_find_next_ext_capability()
264 while (ttl-- > 0) { in dw_pcie_find_next_ext_capability()
329 if (pci->ops && pci->ops->read_dbi) in dw_pcie_read_dbi()
330 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size); in dw_pcie_read_dbi()
332 ret = dw_pcie_read(pci->dbi_base + reg, size, &val); in dw_pcie_read_dbi()
334 dev_err(pci->dev, "Read DBI address failed\n"); in dw_pcie_read_dbi()
344 if (pci->ops && pci->ops->write_dbi) { in dw_pcie_write_dbi()
345 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val); in dw_pcie_write_dbi()
349 ret = dw_pcie_write(pci->dbi_base + reg, size, val); in dw_pcie_write_dbi()
351 dev_err(pci->dev, "Write DBI address failed\n"); in dw_pcie_write_dbi()
359 if (pci->ops && pci->ops->write_dbi2) { in dw_pcie_write_dbi2()
360 pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val); in dw_pcie_write_dbi2()
364 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val); in dw_pcie_write_dbi2()
366 dev_err(pci->dev, "write DBI address failed\n"); in dw_pcie_write_dbi2()
373 return pci->atu_base + PCIE_ATU_UNROLL_BASE(dir, index); in dw_pcie_select_atu()
376 return pci->atu_base; in dw_pcie_select_atu()
387 if (pci->ops && pci->ops->read_dbi) in dw_pcie_readl_atu()
388 return pci->ops->read_dbi(pci, base, reg, 4); in dw_pcie_readl_atu()
392 dev_err(pci->dev, "Read ATU address failed\n"); in dw_pcie_readl_atu()
405 if (pci->ops && pci->ops->write_dbi) { in dw_pcie_writel_atu()
406 pci->ops->write_dbi(pci, base, reg, 4, val); in dw_pcie_writel_atu()
412 dev_err(pci->dev, "Write ATU address failed\n"); in dw_pcie_writel_atu()
430 * bit in the Control register-1 of the ATU outbound region acts in dw_pcie_enable_ecrc()
449 * on Root Port:- TLP Digest (DWord size) gets appended to each packet in dw_pcie_enable_ecrc()
454 * on End Point:- TLP Digest is received for some/all the packets coming in dw_pcie_enable_ecrc()
474 if (pci->ops && pci->ops->cpu_addr_fixup) in __dw_pcie_prog_outbound_atu()
475 cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr); in __dw_pcie_prog_outbound_atu()
477 limit_addr = cpu_addr + size - 1; in __dw_pcie_prog_outbound_atu()
479 if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) || in __dw_pcie_prog_outbound_atu()
480 !IS_ALIGNED(cpu_addr, pci->region_align) || in __dw_pcie_prog_outbound_atu()
481 !IS_ALIGNED(pci_addr, pci->region_align) || !size) { in __dw_pcie_prog_outbound_atu()
482 return -EINVAL; in __dw_pcie_prog_outbound_atu()
523 dev_err(pci->dev, "Outbound iATU is not being enabled\n"); in __dw_pcie_prog_outbound_atu()
525 return -ETIMEDOUT; in __dw_pcie_prog_outbound_atu()
557 u64 limit_addr = pci_addr + size - 1; in dw_pcie_prog_inbound_atu()
560 if ((limit_addr & ~pci->region_limit) != (pci_addr & ~pci->region_limit) || in dw_pcie_prog_inbound_atu()
561 !IS_ALIGNED(cpu_addr, pci->region_align) || in dw_pcie_prog_inbound_atu()
562 !IS_ALIGNED(pci_addr, pci->region_align) || !size) { in dw_pcie_prog_inbound_atu()
563 return -EINVAL; in dw_pcie_prog_inbound_atu()
601 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); in dw_pcie_prog_inbound_atu()
603 return -ETIMEDOUT; in dw_pcie_prog_inbound_atu()
611 if (!IS_ALIGNED(cpu_addr, pci->region_align)) in dw_pcie_prog_ep_inbound_atu()
612 return -EINVAL; in dw_pcie_prog_ep_inbound_atu()
637 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); in dw_pcie_prog_ep_inbound_atu()
639 return -ETIMEDOUT; in dw_pcie_prog_ep_inbound_atu()
661 dev_info(pci->dev, "Phy link never came up\n"); in dw_pcie_wait_for_link()
662 return -ETIMEDOUT; in dw_pcie_wait_for_link()
668 dev_info(pci->dev, "PCIe Gen.%u x%u link up\n", in dw_pcie_wait_for_link()
680 if (pci->ops && pci->ops->link_up) in dw_pcie_link_up()
681 return pci->ops->link_up(pci); in dw_pcie_link_up()
739 u64 max; in dw_pcie_iatu_detect() local
745 max_region = min((int)pci->atu_size / 512, 256); in dw_pcie_iatu_detect()
747 pci->atu_base = pci->dbi_base + PCIE_ATU_VIEWPORT_BASE; in dw_pcie_iatu_detect()
748 pci->atu_size = PCIE_ATU_VIEWPORT_SIZE; in dw_pcie_iatu_detect()
773 dev_err(pci->dev, "No iATU regions found\n"); in dw_pcie_iatu_detect()
782 max = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT); in dw_pcie_iatu_detect()
784 max = 0; in dw_pcie_iatu_detect()
787 pci->num_ob_windows = ob; in dw_pcie_iatu_detect()
788 pci->num_ib_windows = ib; in dw_pcie_iatu_detect()
789 pci->region_align = 1 << fls(min); in dw_pcie_iatu_detect()
790 pci->region_limit = (max << 32) | (SZ_4G - 1); in dw_pcie_iatu_detect()
792 dev_info(pci->dev, "iATU: unroll %s, %u ob, %u ib, align %uK, limit %lluG\n", in dw_pcie_iatu_detect()
794 pci->num_ob_windows, pci->num_ib_windows, in dw_pcie_iatu_detect()
795 pci->region_align / SZ_1K, (pci->region_limit + 1) / SZ_1G); in dw_pcie_iatu_detect()
803 if (pci->ops && pci->ops->read_dbi) in dw_pcie_readl_dma()
804 return pci->ops->read_dbi(pci, pci->edma.reg_base, reg, 4); in dw_pcie_readl_dma()
806 ret = dw_pcie_read(pci->edma.reg_base + reg, 4, &val); in dw_pcie_readl_dma()
808 dev_err(pci->dev, "Read DMA address failed\n"); in dw_pcie_readl_dma()
820 return -EINVAL; in dw_pcie_edma_irq_vector()
849 if (val == 0xFFFFFFFF && pci->edma.reg_base) { in dw_pcie_edma_find_chip()
850 pci->edma.mf = EDMA_MF_EDMA_UNROLL; in dw_pcie_edma_find_chip()
854 pci->edma.mf = EDMA_MF_EDMA_LEGACY; in dw_pcie_edma_find_chip()
856 pci->edma.reg_base = pci->dbi_base + PCIE_DMA_VIEWPORT_BASE; in dw_pcie_edma_find_chip()
858 return -ENODEV; in dw_pcie_edma_find_chip()
861 pci->edma.dev = pci->dev; in dw_pcie_edma_find_chip()
863 if (!pci->edma.ops) in dw_pcie_edma_find_chip()
864 pci->edma.ops = &dw_pcie_edma_ops; in dw_pcie_edma_find_chip()
866 pci->edma.flags |= DW_EDMA_CHIP_LOCAL; in dw_pcie_edma_find_chip()
868 pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val); in dw_pcie_edma_find_chip()
869 pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val); in dw_pcie_edma_find_chip()
872 if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > EDMA_MAX_WR_CH || in dw_pcie_edma_find_chip()
873 !pci->edma.ll_rd_cnt || pci->edma.ll_rd_cnt > EDMA_MAX_RD_CH) in dw_pcie_edma_find_chip()
874 return -EINVAL; in dw_pcie_edma_find_chip()
881 struct platform_device *pdev = to_platform_device(pci->dev); in dw_pcie_edma_irq_verify()
882 u16 ch_cnt = pci->edma.ll_wr_cnt + pci->edma.ll_rd_cnt; in dw_pcie_edma_irq_verify()
886 if (pci->edma.nr_irqs == 1) in dw_pcie_edma_irq_verify()
888 else if (pci->edma.nr_irqs > 1) in dw_pcie_edma_irq_verify()
889 return pci->edma.nr_irqs != ch_cnt ? -EINVAL : 0; in dw_pcie_edma_irq_verify()
893 pci->edma.nr_irqs = 1; in dw_pcie_edma_irq_verify()
897 for (; pci->edma.nr_irqs < ch_cnt; pci->edma.nr_irqs++) { in dw_pcie_edma_irq_verify()
898 snprintf(name, sizeof(name), "dma%d", pci->edma.nr_irqs); in dw_pcie_edma_irq_verify()
902 return -EINVAL; in dw_pcie_edma_irq_verify()
914 for (i = 0; i < pci->edma.ll_wr_cnt; i++) { in dw_pcie_edma_ll_alloc()
915 ll = &pci->edma.ll_region_wr[i]; in dw_pcie_edma_ll_alloc()
916 ll->sz = DMA_LLP_MEM_SIZE; in dw_pcie_edma_ll_alloc()
917 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz, in dw_pcie_edma_ll_alloc()
919 if (!ll->vaddr.mem) in dw_pcie_edma_ll_alloc()
920 return -ENOMEM; in dw_pcie_edma_ll_alloc()
922 ll->paddr = paddr; in dw_pcie_edma_ll_alloc()
925 for (i = 0; i < pci->edma.ll_rd_cnt; i++) { in dw_pcie_edma_ll_alloc()
926 ll = &pci->edma.ll_region_rd[i]; in dw_pcie_edma_ll_alloc()
927 ll->sz = DMA_LLP_MEM_SIZE; in dw_pcie_edma_ll_alloc()
928 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz, in dw_pcie_edma_ll_alloc()
930 if (!ll->vaddr.mem) in dw_pcie_edma_ll_alloc()
931 return -ENOMEM; in dw_pcie_edma_ll_alloc()
933 ll->paddr = paddr; in dw_pcie_edma_ll_alloc()
951 dev_err(pci->dev, "Invalid eDMA IRQs found\n"); in dw_pcie_edma_detect()
957 dev_err(pci->dev, "Couldn't allocate LLP memory\n"); in dw_pcie_edma_detect()
962 ret = dw_edma_probe(&pci->edma); in dw_pcie_edma_detect()
963 if (ret && ret != -ENODEV) { in dw_pcie_edma_detect()
964 dev_err(pci->dev, "Couldn't register eDMA device\n"); in dw_pcie_edma_detect()
968 dev_info(pci->dev, "eDMA: unroll %s, %hu wr, %hu rd\n", in dw_pcie_edma_detect()
969 pci->edma.mf == EDMA_MF_EDMA_UNROLL ? "T" : "F", in dw_pcie_edma_detect()
970 pci->edma.ll_wr_cnt, pci->edma.ll_rd_cnt); in dw_pcie_edma_detect()
977 dw_edma_remove(&pci->edma); in dw_pcie_edma_remove()
984 if (pci->link_gen > 0) in dw_pcie_setup()
985 dw_pcie_link_set_max_speed(pci, pci->link_gen); in dw_pcie_setup()
988 if (pci->n_fts[0]) { in dw_pcie_setup()
991 val |= PORT_AFR_N_FTS(pci->n_fts[0]); in dw_pcie_setup()
992 val |= PORT_AFR_CC_N_FTS(pci->n_fts[0]); in dw_pcie_setup()
997 if (pci->n_fts[1]) { in dw_pcie_setup()
1000 val |= pci->n_fts[1]; in dw_pcie_setup()
1016 if (!pci->num_lanes) { in dw_pcie_setup()
1017 dev_dbg(pci->dev, "Using h/w default number of lanes\n"); in dw_pcie_setup()
1024 switch (pci->num_lanes) { in dw_pcie_setup()
1038 dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->num_lanes); in dw_pcie_setup()
1046 switch (pci->num_lanes) { in dw_pcie_setup()