Lines Matching +full:imx6sx +full:- +full:pcie +full:- +full:ep
1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Freescale i.MX6 SoCs
17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
36 #include "pcie-designware.h"
45 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
49 IMX6SX, enumerator
80 struct clk *pcie; member
97 /* power domain for pcie */
99 /* power domain for pcie phy */
105 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
109 /* PCIe Port Logic registers (memory-mapped) */
122 /* PHY registers (not memory-mapped) */
136 /* iMX7 PCIe PHY registers */
159 WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ && in imx6_pcie_grp_offset()
160 imx6_pcie->drvdata->variant != IMX8MQ_EP && in imx6_pcie_grp_offset()
161 imx6_pcie->drvdata->variant != IMX8MM && in imx6_pcie_grp_offset()
162 imx6_pcie->drvdata->variant != IMX8MM_EP && in imx6_pcie_grp_offset()
163 imx6_pcie->drvdata->variant != IMX8MP && in imx6_pcie_grp_offset()
164 imx6_pcie->drvdata->variant != IMX8MP_EP); in imx6_pcie_grp_offset()
165 return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; in imx6_pcie_grp_offset()
172 if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) in imx6_pcie_configure_type()
177 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_configure_type()
180 if (imx6_pcie->controller_id == 1) { in imx6_pcie_configure_type()
195 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val); in imx6_pcie_configure_type()
200 struct dw_pcie *pci = imx6_pcie->pci; in pcie_phy_poll_ack()
216 return -ETIMEDOUT; in pcie_phy_poll_ack()
221 struct dw_pcie *pci = imx6_pcie->pci; in pcie_phy_wait_ack()
241 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
244 struct dw_pcie *pci = imx6_pcie->pci; in pcie_phy_read()
270 struct dw_pcie *pci = imx6_pcie->pci; in pcie_phy_write()
295 /* wait for ack de-assertion */ in pcie_phy_write()
313 /* wait for ack de-assertion */ in pcie_phy_write()
325 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_init_phy()
341 regmap_update_bits(imx6_pcie->iomuxc_gpr, in imx6_pcie_init_phy()
350 if (imx6_pcie->vph && in imx6_pcie_init_phy()
351 regulator_get_voltage(imx6_pcie->vph) > 3000000) in imx6_pcie_init_phy()
352 regmap_update_bits(imx6_pcie->iomuxc_gpr, in imx6_pcie_init_phy()
358 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_init_phy()
361 case IMX6SX: in imx6_pcie_init_phy()
362 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_init_phy()
367 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_init_phy()
370 /* configure constant input signal to the pcie ctrl and phy */ in imx6_pcie_init_phy()
371 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_init_phy()
374 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx6_pcie_init_phy()
376 imx6_pcie->tx_deemph_gen1 << 0); in imx6_pcie_init_phy()
377 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx6_pcie_init_phy()
379 imx6_pcie->tx_deemph_gen2_3p5db << 6); in imx6_pcie_init_phy()
380 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx6_pcie_init_phy()
382 imx6_pcie->tx_deemph_gen2_6db << 12); in imx6_pcie_init_phy()
383 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx6_pcie_init_phy()
385 imx6_pcie->tx_swing_full << 18); in imx6_pcie_init_phy()
386 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx6_pcie_init_phy()
388 imx6_pcie->tx_swing_low << 25); in imx6_pcie_init_phy()
398 struct device *dev = imx6_pcie->pci->dev; in imx7d_pcie_wait_for_phy_pll_lock()
400 if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr, in imx7d_pcie_wait_for_phy_pll_lock()
405 dev_err(dev, "PCIe PLL lock timeout\n"); in imx7d_pcie_wait_for_phy_pll_lock()
410 unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy); in imx6_setup_phy_mpll()
414 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) in imx6_setup_phy_mpll()
433 dev_err(imx6_pcie->pci->dev, in imx6_setup_phy_mpll()
435 return -EINVAL; in imx6_setup_phy_mpll()
459 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) in imx6_pcie_reset_phy()
486 * make it look like it read all-ones. in imx6q_pcie_abort_handler()
494 val = -1; in imx6q_pcie_abort_handler()
496 regs->uregs[reg] = val; in imx6q_pcie_abort_handler()
497 regs->ARM_pc += 4; in imx6q_pcie_abort_handler()
502 regs->uregs[reg] = -1; in imx6q_pcie_abort_handler()
503 regs->ARM_pc += 4; in imx6q_pcie_abort_handler()
517 if (dev->pm_domain) in imx6_pcie_attach_pd()
520 imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie"); in imx6_pcie_attach_pd()
521 if (IS_ERR(imx6_pcie->pd_pcie)) in imx6_pcie_attach_pd()
522 return PTR_ERR(imx6_pcie->pd_pcie); in imx6_pcie_attach_pd()
524 if (!imx6_pcie->pd_pcie) in imx6_pcie_attach_pd()
526 link = device_link_add(dev, imx6_pcie->pd_pcie, in imx6_pcie_attach_pd()
531 dev_err(dev, "Failed to add device_link to pcie pd.\n"); in imx6_pcie_attach_pd()
532 return -EINVAL; in imx6_pcie_attach_pd()
535 imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy"); in imx6_pcie_attach_pd()
536 if (IS_ERR(imx6_pcie->pd_pcie_phy)) in imx6_pcie_attach_pd()
537 return PTR_ERR(imx6_pcie->pd_pcie_phy); in imx6_pcie_attach_pd()
539 link = device_link_add(dev, imx6_pcie->pd_pcie_phy, in imx6_pcie_attach_pd()
545 return -EINVAL; in imx6_pcie_attach_pd()
553 struct dw_pcie *pci = imx6_pcie->pci; in imx6_pcie_enable_ref_clk()
554 struct device *dev = pci->dev; in imx6_pcie_enable_ref_clk()
558 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_enable_ref_clk()
559 case IMX6SX: in imx6_pcie_enable_ref_clk()
560 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi); in imx6_pcie_enable_ref_clk()
566 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_enable_ref_clk()
572 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, in imx6_pcie_enable_ref_clk()
581 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, in imx6_pcie_enable_ref_clk()
592 ret = clk_prepare_enable(imx6_pcie->pcie_aux); in imx6_pcie_enable_ref_clk()
603 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, in imx6_pcie_enable_ref_clk()
606 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, in imx6_pcie_enable_ref_clk()
617 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_disable_ref_clk()
618 case IMX6SX: in imx6_pcie_disable_ref_clk()
619 clk_disable_unprepare(imx6_pcie->pcie_inbound_axi); in imx6_pcie_disable_ref_clk()
623 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, in imx6_pcie_disable_ref_clk()
625 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, in imx6_pcie_disable_ref_clk()
630 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_disable_ref_clk()
640 clk_disable_unprepare(imx6_pcie->pcie_aux); in imx6_pcie_disable_ref_clk()
649 struct dw_pcie *pci = imx6_pcie->pci; in imx6_pcie_clk_enable()
650 struct device *dev = pci->dev; in imx6_pcie_clk_enable()
653 ret = clk_prepare_enable(imx6_pcie->pcie_phy); in imx6_pcie_clk_enable()
659 ret = clk_prepare_enable(imx6_pcie->pcie_bus); in imx6_pcie_clk_enable()
665 ret = clk_prepare_enable(imx6_pcie->pcie); in imx6_pcie_clk_enable()
667 dev_err(dev, "unable to enable pcie clock\n"); in imx6_pcie_clk_enable()
673 dev_err(dev, "unable to enable pcie ref clock\n"); in imx6_pcie_clk_enable()
682 clk_disable_unprepare(imx6_pcie->pcie); in imx6_pcie_clk_enable()
684 clk_disable_unprepare(imx6_pcie->pcie_bus); in imx6_pcie_clk_enable()
686 clk_disable_unprepare(imx6_pcie->pcie_phy); in imx6_pcie_clk_enable()
694 clk_disable_unprepare(imx6_pcie->pcie); in imx6_pcie_clk_disable()
695 clk_disable_unprepare(imx6_pcie->pcie_bus); in imx6_pcie_clk_disable()
696 clk_disable_unprepare(imx6_pcie->pcie_phy); in imx6_pcie_clk_disable()
701 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_assert_core_reset()
705 reset_control_assert(imx6_pcie->pciephy_reset); in imx6_pcie_assert_core_reset()
711 reset_control_assert(imx6_pcie->apps_reset); in imx6_pcie_assert_core_reset()
713 case IMX6SX: in imx6_pcie_assert_core_reset()
714 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_assert_core_reset()
717 /* Force PCIe PHY reset */ in imx6_pcie_assert_core_reset()
718 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, in imx6_pcie_assert_core_reset()
723 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, in imx6_pcie_assert_core_reset()
728 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, in imx6_pcie_assert_core_reset()
730 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, in imx6_pcie_assert_core_reset()
735 /* Some boards don't have PCIe reset GPIO. */ in imx6_pcie_assert_core_reset()
736 if (gpio_is_valid(imx6_pcie->reset_gpio)) in imx6_pcie_assert_core_reset()
737 gpio_set_value_cansleep(imx6_pcie->reset_gpio, in imx6_pcie_assert_core_reset()
738 imx6_pcie->gpio_active_high); in imx6_pcie_assert_core_reset()
743 struct dw_pcie *pci = imx6_pcie->pci; in imx6_pcie_deassert_core_reset()
744 struct device *dev = pci->dev; in imx6_pcie_deassert_core_reset()
746 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_deassert_core_reset()
749 reset_control_deassert(imx6_pcie->pciephy_reset); in imx6_pcie_deassert_core_reset()
752 reset_control_deassert(imx6_pcie->pciephy_reset); in imx6_pcie_deassert_core_reset()
754 /* Workaround for ERR010728, failure of PCI-e PLL VCO to in imx6_pcie_deassert_core_reset()
755 * oscillate, especially when cold. This turns off "Duty-cycle in imx6_pcie_deassert_core_reset()
758 if (likely(imx6_pcie->phy_base)) { in imx6_pcie_deassert_core_reset()
759 /* De-assert DCC_FB_EN */ in imx6_pcie_deassert_core_reset()
761 imx6_pcie->phy_base + PCIE_PHY_CMN_REG4); in imx6_pcie_deassert_core_reset()
765 imx6_pcie->phy_base + PCIE_PHY_CMN_REG24); in imx6_pcie_deassert_core_reset()
768 imx6_pcie->phy_base + PCIE_PHY_CMN_REG26); in imx6_pcie_deassert_core_reset()
770 dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); in imx6_pcie_deassert_core_reset()
775 case IMX6SX: in imx6_pcie_deassert_core_reset()
776 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, in imx6_pcie_deassert_core_reset()
780 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, in imx6_pcie_deassert_core_reset()
793 /* Some boards don't have PCIe reset GPIO. */ in imx6_pcie_deassert_core_reset()
794 if (gpio_is_valid(imx6_pcie->reset_gpio)) { in imx6_pcie_deassert_core_reset()
796 gpio_set_value_cansleep(imx6_pcie->reset_gpio, in imx6_pcie_deassert_core_reset()
797 !imx6_pcie->gpio_active_high); in imx6_pcie_deassert_core_reset()
798 /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */ in imx6_pcie_deassert_core_reset()
807 struct dw_pcie *pci = imx6_pcie->pci; in imx6_pcie_wait_for_speed_change()
808 struct device *dev = pci->dev; in imx6_pcie_wait_for_speed_change()
821 return -ETIMEDOUT; in imx6_pcie_wait_for_speed_change()
828 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_ltssm_enable()
830 case IMX6SX: in imx6_pcie_ltssm_enable()
832 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_ltssm_enable()
843 reset_control_deassert(imx6_pcie->apps_reset); in imx6_pcie_ltssm_enable()
852 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_ltssm_disable()
854 case IMX6SX: in imx6_pcie_ltssm_disable()
856 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_ltssm_disable()
866 reset_control_assert(imx6_pcie->apps_reset); in imx6_pcie_ltssm_disable()
874 struct device *dev = pci->dev; in imx6_pcie_start_link()
882 * bus will not be detected at all. This happens with PCIe switches. in imx6_pcie_start_link()
898 if (pci->link_gen > 1) { in imx6_pcie_start_link()
903 tmp |= pci->link_gen; in imx6_pcie_start_link()
915 if (imx6_pcie->drvdata->flags & in imx6_pcie_start_link()
920 * occurs and we go Gen1 -> yep, Gen1. The difference in imx6_pcie_start_link()
941 imx6_pcie->link_is_up = true; in imx6_pcie_start_link()
947 imx6_pcie->link_is_up = false; in imx6_pcie_start_link()
957 struct device *dev = pci->dev; in imx6_pcie_stop_link()
959 /* Turn off PCIe LTSSM */ in imx6_pcie_stop_link()
966 struct device *dev = pci->dev; in imx6_pcie_host_init()
970 if (imx6_pcie->vpcie) { in imx6_pcie_host_init()
971 ret = regulator_enable(imx6_pcie->vpcie); in imx6_pcie_host_init()
984 dev_err(dev, "unable to enable pcie clocks: %d\n", ret); in imx6_pcie_host_init()
988 if (imx6_pcie->phy) { in imx6_pcie_host_init()
989 ret = phy_init(imx6_pcie->phy); in imx6_pcie_host_init()
991 dev_err(dev, "pcie PHY power up failed\n"); in imx6_pcie_host_init()
996 if (imx6_pcie->phy) { in imx6_pcie_host_init()
997 ret = phy_power_on(imx6_pcie->phy); in imx6_pcie_host_init()
1006 dev_err(dev, "pcie deassert core reset failed: %d\n", ret); in imx6_pcie_host_init()
1015 if (imx6_pcie->phy) in imx6_pcie_host_init()
1016 phy_exit(imx6_pcie->phy); in imx6_pcie_host_init()
1020 if (imx6_pcie->vpcie) in imx6_pcie_host_init()
1021 regulator_disable(imx6_pcie->vpcie); in imx6_pcie_host_init()
1030 if (imx6_pcie->phy) { in imx6_pcie_host_exit()
1031 if (phy_power_off(imx6_pcie->phy)) in imx6_pcie_host_exit()
1032 dev_err(pci->dev, "unable to power off PHY\n"); in imx6_pcie_host_exit()
1033 phy_exit(imx6_pcie->phy); in imx6_pcie_host_exit()
1037 if (imx6_pcie->vpcie) in imx6_pcie_host_exit()
1038 regulator_disable(imx6_pcie->vpcie); in imx6_pcie_host_exit()
1051 static void imx6_pcie_ep_init(struct dw_pcie_ep *ep) in imx6_pcie_ep_init() argument
1054 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); in imx6_pcie_ep_init()
1060 static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, in imx6_pcie_ep_raise_irq() argument
1064 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); in imx6_pcie_ep_raise_irq()
1068 return dw_pcie_ep_raise_legacy_irq(ep, func_no); in imx6_pcie_ep_raise_irq()
1070 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); in imx6_pcie_ep_raise_irq()
1072 return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); in imx6_pcie_ep_raise_irq()
1074 dev_err(pci->dev, "UNKNOWN IRQ type\n"); in imx6_pcie_ep_raise_irq()
1075 return -EINVAL; in imx6_pcie_ep_raise_irq()
1090 imx6_pcie_ep_get_features(struct dw_pcie_ep *ep) in imx6_pcie_ep_get_features() argument
1106 struct dw_pcie_ep *ep; in imx6_add_pcie_ep() local
1108 struct dw_pcie *pci = imx6_pcie->pci; in imx6_add_pcie_ep()
1109 struct dw_pcie_rp *pp = &pci->pp; in imx6_add_pcie_ep()
1110 struct device *dev = pci->dev; in imx6_add_pcie_ep()
1113 ep = &pci->ep; in imx6_add_pcie_ep()
1114 ep->ops = &pcie_ep_ops; in imx6_add_pcie_ep()
1116 switch (imx6_pcie->drvdata->variant) { in imx6_add_pcie_ep()
1126 pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset; in imx6_add_pcie_ep()
1129 return -EINVAL; in imx6_add_pcie_ep()
1131 ep->phys_base = res->start; in imx6_add_pcie_ep()
1132 ep->addr_size = resource_size(res); in imx6_add_pcie_ep()
1133 ep->page_size = SZ_64K; in imx6_add_pcie_ep()
1135 ret = dw_pcie_ep_init(ep); in imx6_add_pcie_ep()
1148 struct device *dev = imx6_pcie->pci->dev; in imx6_pcie_pm_turnoff()
1151 if (imx6_pcie->turnoff_reset) { in imx6_pcie_pm_turnoff()
1152 reset_control_assert(imx6_pcie->turnoff_reset); in imx6_pcie_pm_turnoff()
1153 reset_control_deassert(imx6_pcie->turnoff_reset); in imx6_pcie_pm_turnoff()
1158 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_pm_turnoff()
1159 case IMX6SX: in imx6_pcie_pm_turnoff()
1161 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_pm_turnoff()
1164 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_pm_turnoff()
1176 * The standard recommends a 1-10ms timeout after which to in imx6_pcie_pm_turnoff()
1187 struct dw_pcie *pci = imx6_pcie->pci; in imx6_pcie_msi_save_restore()
1193 imx6_pcie->msi_ctrl = val; in imx6_pcie_msi_save_restore()
1196 val = imx6_pcie->msi_ctrl; in imx6_pcie_msi_save_restore()
1206 struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; in imx6_pcie_suspend_noirq()
1208 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) in imx6_pcie_suspend_noirq()
1213 imx6_pcie_stop_link(imx6_pcie->pci); in imx6_pcie_suspend_noirq()
1223 struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; in imx6_pcie_resume_noirq()
1225 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) in imx6_pcie_resume_noirq()
1234 if (imx6_pcie->link_is_up) in imx6_pcie_resume_noirq()
1235 imx6_pcie_start_link(imx6_pcie->pci); in imx6_pcie_resume_noirq()
1247 struct device *dev = &pdev->dev; in imx6_pcie_probe()
1252 struct device_node *node = dev->of_node; in imx6_pcie_probe()
1258 return -ENOMEM; in imx6_pcie_probe()
1262 return -ENOMEM; in imx6_pcie_probe()
1264 pci->dev = dev; in imx6_pcie_probe()
1265 pci->ops = &dw_pcie_ops; in imx6_pcie_probe()
1266 pci->pp.ops = &imx6_pcie_host_ops; in imx6_pcie_probe()
1268 imx6_pcie->pci = pci; in imx6_pcie_probe()
1269 imx6_pcie->drvdata = of_device_get_match_data(dev); in imx6_pcie_probe()
1272 np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); in imx6_pcie_probe()
1278 dev_err(dev, "Unable to map PCIe PHY\n"); in imx6_pcie_probe()
1281 imx6_pcie->phy_base = devm_ioremap_resource(dev, &res); in imx6_pcie_probe()
1282 if (IS_ERR(imx6_pcie->phy_base)) in imx6_pcie_probe()
1283 return PTR_ERR(imx6_pcie->phy_base); in imx6_pcie_probe()
1286 pci->dbi_base = devm_platform_get_and_ioremap_resource(pdev, 0, &dbi_base); in imx6_pcie_probe()
1287 if (IS_ERR(pci->dbi_base)) in imx6_pcie_probe()
1288 return PTR_ERR(pci->dbi_base); in imx6_pcie_probe()
1291 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0); in imx6_pcie_probe()
1292 imx6_pcie->gpio_active_high = of_property_read_bool(node, in imx6_pcie_probe()
1293 "reset-gpio-active-high"); in imx6_pcie_probe()
1294 if (gpio_is_valid(imx6_pcie->reset_gpio)) { in imx6_pcie_probe()
1295 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio, in imx6_pcie_probe()
1296 imx6_pcie->gpio_active_high ? in imx6_pcie_probe()
1299 "PCIe reset"); in imx6_pcie_probe()
1304 } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) { in imx6_pcie_probe()
1305 return imx6_pcie->reset_gpio; in imx6_pcie_probe()
1309 imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus"); in imx6_pcie_probe()
1310 if (IS_ERR(imx6_pcie->pcie_bus)) in imx6_pcie_probe()
1311 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_bus), in imx6_pcie_probe()
1314 imx6_pcie->pcie = devm_clk_get(dev, "pcie"); in imx6_pcie_probe()
1315 if (IS_ERR(imx6_pcie->pcie)) in imx6_pcie_probe()
1316 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie), in imx6_pcie_probe()
1317 "pcie clock source missing or invalid\n"); in imx6_pcie_probe()
1319 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_probe()
1320 case IMX6SX: in imx6_pcie_probe()
1321 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev, in imx6_pcie_probe()
1323 if (IS_ERR(imx6_pcie->pcie_inbound_axi)) in imx6_pcie_probe()
1324 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_inbound_axi), in imx6_pcie_probe()
1329 imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux"); in imx6_pcie_probe()
1330 if (IS_ERR(imx6_pcie->pcie_aux)) in imx6_pcie_probe()
1331 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux), in imx6_pcie_probe()
1335 if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) in imx6_pcie_probe()
1336 imx6_pcie->controller_id = 1; in imx6_pcie_probe()
1338 imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, in imx6_pcie_probe()
1340 if (IS_ERR(imx6_pcie->pciephy_reset)) { in imx6_pcie_probe()
1342 return PTR_ERR(imx6_pcie->pciephy_reset); in imx6_pcie_probe()
1345 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, in imx6_pcie_probe()
1347 if (IS_ERR(imx6_pcie->apps_reset)) { in imx6_pcie_probe()
1348 dev_err(dev, "Failed to get PCIE APPS reset control\n"); in imx6_pcie_probe()
1349 return PTR_ERR(imx6_pcie->apps_reset); in imx6_pcie_probe()
1356 imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux"); in imx6_pcie_probe()
1357 if (IS_ERR(imx6_pcie->pcie_aux)) in imx6_pcie_probe()
1358 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux), in imx6_pcie_probe()
1360 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, in imx6_pcie_probe()
1362 if (IS_ERR(imx6_pcie->apps_reset)) in imx6_pcie_probe()
1363 return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), in imx6_pcie_probe()
1364 "failed to get pcie apps reset control\n"); in imx6_pcie_probe()
1366 imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); in imx6_pcie_probe()
1367 if (IS_ERR(imx6_pcie->phy)) in imx6_pcie_probe()
1368 return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), in imx6_pcie_probe()
1369 "failed to get pcie phy\n"); in imx6_pcie_probe()
1376 if (imx6_pcie->phy == NULL) { in imx6_pcie_probe()
1377 imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy"); in imx6_pcie_probe()
1378 if (IS_ERR(imx6_pcie->pcie_phy)) in imx6_pcie_probe()
1379 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_phy), in imx6_pcie_probe()
1385 imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); in imx6_pcie_probe()
1386 if (IS_ERR(imx6_pcie->turnoff_reset)) { in imx6_pcie_probe()
1388 return PTR_ERR(imx6_pcie->turnoff_reset); in imx6_pcie_probe()
1392 imx6_pcie->iomuxc_gpr = in imx6_pcie_probe()
1393 syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr); in imx6_pcie_probe()
1394 if (IS_ERR(imx6_pcie->iomuxc_gpr)) { in imx6_pcie_probe()
1396 return PTR_ERR(imx6_pcie->iomuxc_gpr); in imx6_pcie_probe()
1399 /* Grab PCIe PHY Tx Settings */ in imx6_pcie_probe()
1400 if (of_property_read_u32(node, "fsl,tx-deemph-gen1", in imx6_pcie_probe()
1401 &imx6_pcie->tx_deemph_gen1)) in imx6_pcie_probe()
1402 imx6_pcie->tx_deemph_gen1 = 0; in imx6_pcie_probe()
1404 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db", in imx6_pcie_probe()
1405 &imx6_pcie->tx_deemph_gen2_3p5db)) in imx6_pcie_probe()
1406 imx6_pcie->tx_deemph_gen2_3p5db = 0; in imx6_pcie_probe()
1408 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db", in imx6_pcie_probe()
1409 &imx6_pcie->tx_deemph_gen2_6db)) in imx6_pcie_probe()
1410 imx6_pcie->tx_deemph_gen2_6db = 20; in imx6_pcie_probe()
1412 if (of_property_read_u32(node, "fsl,tx-swing-full", in imx6_pcie_probe()
1413 &imx6_pcie->tx_swing_full)) in imx6_pcie_probe()
1414 imx6_pcie->tx_swing_full = 127; in imx6_pcie_probe()
1416 if (of_property_read_u32(node, "fsl,tx-swing-low", in imx6_pcie_probe()
1417 &imx6_pcie->tx_swing_low)) in imx6_pcie_probe()
1418 imx6_pcie->tx_swing_low = 127; in imx6_pcie_probe()
1421 pci->link_gen = 1; in imx6_pcie_probe()
1422 of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen); in imx6_pcie_probe()
1424 imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); in imx6_pcie_probe()
1425 if (IS_ERR(imx6_pcie->vpcie)) { in imx6_pcie_probe()
1426 if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV) in imx6_pcie_probe()
1427 return PTR_ERR(imx6_pcie->vpcie); in imx6_pcie_probe()
1428 imx6_pcie->vpcie = NULL; in imx6_pcie_probe()
1431 imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph"); in imx6_pcie_probe()
1432 if (IS_ERR(imx6_pcie->vph)) { in imx6_pcie_probe()
1433 if (PTR_ERR(imx6_pcie->vph) != -ENODEV) in imx6_pcie_probe()
1434 return PTR_ERR(imx6_pcie->vph); in imx6_pcie_probe()
1435 imx6_pcie->vph = NULL; in imx6_pcie_probe()
1444 if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) { in imx6_pcie_probe()
1449 ret = dw_pcie_host_init(&pci->pp); in imx6_pcie_probe()
1479 .gpr = "fsl,imx6q-iomuxc-gpr",
1481 [IMX6SX] = {
1482 .variant = IMX6SX,
1486 .gpr = "fsl,imx6q-iomuxc-gpr",
1494 .gpr = "fsl,imx6q-iomuxc-gpr",
1499 .gpr = "fsl,imx7d-iomuxc-gpr",
1503 .gpr = "fsl,imx8mq-iomuxc-gpr",
1508 .gpr = "fsl,imx8mm-iomuxc-gpr",
1513 .gpr = "fsl,imx8mp-iomuxc-gpr",
1518 .gpr = "fsl,imx8mq-iomuxc-gpr",
1523 .gpr = "fsl,imx8mm-iomuxc-gpr",
1528 .gpr = "fsl,imx8mp-iomuxc-gpr",
1533 { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], },
1534 { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
1535 { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
1536 { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
1537 { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
1538 { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
1539 { .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
1540 { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], },
1541 { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], },
1542 { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], },
1548 .name = "imx6q-pcie",
1560 struct pci_bus *bus = dev->bus; in imx6_pcie_quirk()
1561 struct dw_pcie_rp *pp = bus->sysdata; in imx6_pcie_quirk()
1564 if (!bus->dev.parent || !bus->dev.parent->parent) in imx6_pcie_quirk()
1568 if (bus->dev.parent->parent->driver != &imx6_pcie_driver.driver) in imx6_pcie_quirk()
1579 if (imx6_pcie->drvdata->dbi_length) { in imx6_pcie_quirk()
1580 dev->cfg_size = imx6_pcie->drvdata->dbi_length; in imx6_pcie_quirk()
1581 dev_info(&dev->dev, "Limiting cfg_size to %d\n", in imx6_pcie_quirk()
1582 dev->cfg_size); in imx6_pcie_quirk()
1596 return -ENODEV; in imx6_pcie_init()
1602 * by kernel and since imx6q_pcie_abort_handler() is a no-op, in imx6_pcie_init()
1607 "external abort on non-linefetch"); in imx6_pcie_init()