Lines Matching +full:4 +full:- +full:31

1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020  Realtek Corporation
22 #define B_AX_SOP_ASWRM BIT(31)
63 #define B_AX_EF_MODE_SEL_MASK GENMASK(31, 30)
70 #define B_AX_EF_ENT BIT(31)
98 #define B_AX_EROM_EN BIT(4)
103 #define B_AX_DBG_SEL1_4BIT GENMASK(31, 30)
124 #define B_AX_FORCED_IB_EN BIT(4)
145 #define B_AX_TOGGLE BIT(31)
153 #define B_AX_DEBUG_ST_MASK GENMASK(31, 0)
168 #define B_AX_PCIE_MIO_DATA_MASK GENMASK(31, 0)
180 #define MAC_AX_HCI_SEL_MULTI_SDIO 4
211 #define B_AX_EN_32K BIT(31)
215 #define B_AX_UDM1_MASK GENMASK(31, 16)
218 #define B_AX_UDM1_WCPU_C2H_ENQ_CNT_MASK GENMASK(7, 4)
238 #define B_AX_WL_XTAL_SI_CMD_POLL BIT(31)
253 #define B_AX_XTAL_SC_LPS BIT(31)
267 #define B_AX_PINMUX_EESK_FUNC_SEL_MASK GENMASK(7, 4)
270 #define B_AX_PINMUX_GPIO17_FUNC_SEL_MASK GENMASK(7, 4)
297 #define B_AX_SDIO_HCISYS_PWR_STE_MASK GENMASK(5, 4)
302 #define B_AX_C3_L1_MASK GENMASK(5, 4)
316 #define B_AX_WD_ITVL_IDLE_V1_MASK GENMASK(31, 28)
329 #define B_AX_FLUSH_AXI_MST BIT(4)
391 #define B_AX_LTR_DRV_DEC_EN BIT(4)
487 #define B_AX_DMAC_CRPRT BIT(31)
524 #define PCI_LTR_IDLE_TIMER_400US 4
545 #define B_AX_APP_LTR_IDLE BIT(4)
559 #define B_AX_L0_TO_L1_EVENT_MASK GENMASK(31, 28)
577 #define B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 BIT(4)
590 #define B_AX_PLE_EMPTY_QUE_DMAC_CPUIO BIT(4)
603 #define B_AX_WDE_DLE_ERR_INT_EN BIT(4)
608 #define DMAC_ERR_IMR_EN GENMASK(31, 0)
622 #define B_AX_WDE_DLE_ERR_FLAG BIT(4)
638 #define B_AX_HDT_RX_WRITE_UNDERFLOW_INT_EN BIT(31)
663 #define B_AX_HDT_PERMU_UNDERFLOW_INT_EN BIT(4)
703 #define B_AX_HR_WRFF_UNDERFLOW_ERR_INT_EN BIT(31)
728 #define B_AX_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4)
770 #define B_AX_CPU_RX_WRITE_UNDERFLOW_INT_EN BIT(31)
794 #define B_AX_CPU_PERMU_UNDERFLOW_INT_EN BIT(4)
855 #define B_AX_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4)
908 #define B_AX_WDE_OUTPUT_ERR_INT_EN BIT(4)
932 #define B_AX_REUSE_SIZE_ERR_INT_EN BIT(31)
996 #define B_AX_DISPATCHER_INTN_SEL_MASK GENMASK(7, 4)
1006 #define B_AX_HCI_FC_WD_FULL_COND_MASK GENMASK(5, 4)
1017 #define B_AX_GRP BIT(31)
1081 #define B_AX_WDE_ERR_FLAG_MSG_MASK GENMASK(31, 0)
1084 #define B_AX_WDE_ERR_FLAG_NUM1_VLD BIT(31)
1107 #define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(4)
1168 #define B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 BIT(4)
1237 #define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR BIT(4)
1256 #define B_AX_DLE_QEMPTY_GRP GENMASK(31, 0)
1263 #define B_AX_WDE_DFI_ACTIVE BIT(31)
1267 #define B_AX_WDE_DFI_DATA_MASK GENMASK(31, 0)
1278 #define B_AX_PLE_LOCKEN_DLEPIF04 BIT(4)
1288 #define B_AX_PLE_LOCKON_DLEPIF04 BIT(4)
1295 #define B_AX_PLE_ERR_FLAG_NUM1_VLD BIT(31)
1303 #define B_AX_PLE_ERR_FLAG_MSG_MASK GENMASK(31, 0)
1311 #define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 BIT(4)
1322 #define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_V1 BIT(4)
1343 #define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(4)
1393 #define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 BIT(4)
1469 #define B_AX_PLE_DFI_ACTIVE BIT(31)
1473 #define B_AX_PLE_DFI_DATA_MASK GENMASK(31, 0)
1495 #define B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN BIT(4)
1543 #define B_AX_BBPRT_CHIF_LEFT1_ERR_V1 BIT(4)
1553 #define B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN BIT(4)
1579 #define B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN BIT(4)
1609 #define B_AX_WD_BUF_REQ_EXEC BIT(31)
1615 #define B_AX_WD_BUF_STAT_DONE BIT(31)
1621 #define B_AX_WD_CPUQ_OP_EXEC BIT(31)
1640 #define B_AX_WD_CPUQ_OP_STAT_DONE BIT(31)
1646 #define B_AX_WDEQUE_OP_ERR_INT_EN BIT(4)
1676 #define B_AX_TX_OFFSET_ERR_INT_EN BIT(4)
1725 #define B_AX_UC_MGNT_DEC BIT(4)
1743 #define B_AX_TX_TIMEOUT_SEL_MASK GENMASK(31, 30)
1765 #define B_AX_SS_INIT_DONE_1 BIT(31)
1771 #define B_AX_SS_UL_REL BIT(31)
1780 #define B_AX_SS_MACID31_0_PAUSE_MASK GENMASK(31, 0)
1784 #define B_AX_SS_MACID63_32_PAUSE_MASK GENMASK(31, 0)
1788 #define B_AX_SS_MACID95_64_PAUSE_MASK GENMASK(31, 0)
1792 #define B_AX_SS_MACID127_96_PAUSE_MASK GENMASK(31, 0)
1843 #define B_AX_DFI_ACTIVE BIT(31)
1847 #define B_AX_DFI_DATA_MASK GENMASK(31, 0)
1850 #define B_AX_B0_PRELD_FEN BIT(31)
1855 #define B_AX_B0_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
1914 #define B_AX_B0_ISR_ERR_USRCTL_EVT4 BIT(4)
1921 #define B_AX_B1_PRELD_FEN BIT(31)
1923 #define PRELD_B1_ENT_NUM 4
1925 #define B_AX_B1_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
1983 #define B_AX_B1_ISR_ERR_USRCTL_EVT4 BIT(4)
1991 #define B_AX_R_SYM_WLCMAC1_P4_PC_EN BIT(4)
2007 #define B_AX_CMAC_CRPRT BIT(31)
2013 #define B_AX_CMAC_DMA_EN BIT(4)
2021 #define B_AX_CMAC_ALLCKEN GENMASK(31, 0)
2024 #define B_AX_CMAC_DMA_CKEN BIT(4)
2054 #define B_AX_TXSC_40M_MASK GENMASK(7, 4)
2069 #define B_AX_PHYINTF_ERR_IND_EN BIT(4)
2073 #define CMAC0_ERR_IMR_EN GENMASK(31, 0)
2074 #define CMAC1_ERR_IMR_EN GENMASK(31, 0)
2083 #define B_AX_PHYINTF_ERR_IND BIT(4)
2108 #define B_AX_MACID31_0_SLEEP_MASK GENMASK(31, 0)
2113 #define B_AX_MACID63_32_SLEEP_MASK GENMASK(31, 0)
2118 #define B_AX_MACID95_64_SLEEP_MASK GENMASK(31, 0)
2123 #define B_AX_MACID127_96_SLEEP_MASK GENMASK(31, 0)
2128 #define B_AX_PREBKF_TIME_MASK GENMASK(4, 0)
2143 #define B_AX_EDCCA_EN BIT(4)
2162 #define B_AX_CTN_TXEN_BE_1 BIT(4)
2171 #define B_AX_MUEDCA_BE_PARAM_0_TIMER_MASK GENMASK(31, 16)
2185 #define B_AX_SET_MUEDCATIMER_TF_0 BIT(4)
2190 #define B_AX_TB_CHK_TX_NAV BIT(31)
2208 #define B_AX_CTN_CHK_EDCCA BIT(4)
2235 #define B_AX_SCHEDULER_DBG_MASK GENMASK(31, 0)
2257 #define B_AX_RX_BSSID_FIT_EN BIT(4)
2322 #define B_AX_BCN_ERR_CNT_SUM_MASK GENMASK(31, 24)
2334 #define B_AX_BCN_ERR_FLAG_TXON BIT(4)
2362 #define B_AX_BCN_CNT_TMR_MASK GENMASK(31, 0)
2369 #define B_AX_TSFTR_LOW_MASK GENMASK(31, 0)
2376 #define B_AX_TSFTR_HIGH_MASK GENMASK(31, 0)
2393 #define B_AX_P0MB4_EN BIT(4)
2409 #define B_AX_PTCL_TRIGGER_SS_EN_UL BIT(4)
2416 #define B_AX_AMPDU_MAX_TIME_MASK GENMASK(31, 24)
2423 #define B_AX_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16)
2430 #define B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24)
2436 #define S_AX_CTS2S_TH_1K 4
2441 #define B_AX_BAND_MODE BIT(4)
2448 #define B_AX_ADD_TXCNT_BY BIT(31)
2465 #define B_AX_SPE_RPT_PATH_MASK GENMASK(5, 4)
2473 #define B_AX_BT_PLT_PKT_CNT_MASK GENMASK(31, 16)
2479 #define B_AX_RX_PLT_GNT_WL BIT(4)
2498 #define B_AX_F2PCMD_PKTID_ERR_INT_EN BIT(31)
2516 #define B_AX_PTCL_IMR_CLR_ALL GENMASK(31, 0)
2557 #define B_AX_PTCL_DBG_INFO_MASK GENMASK(31, 0)
2576 #define B_AX_RX_GET_NO_PAGE_ERR BIT(31)
2603 #define B_AX_PLE_WD_OPT_FSM_HANG BIT(4)
2611 #define B_AX_RXDMA_DBGOUT_EN BIT(31)
2622 #define B_AX_CSI_PTR_FULL_MODE BIT(4)
2633 #define B_AX_DLE_CLOCK_FORCE_V1 BIT(31)
2645 #define B_AX_RXSTS_FULL_RSV_DEPTH_V1_MASK GENMASK(4, 2)
2650 #define B_AX_RXDMA_TXRPT_QUEUE_ID_SW_EN BIT(31)
2657 #define B_AX_RXDMA_F2PCMD_QUEUE_ID_TGT_SW_1_MASK GENMASK(9, 4)
2664 #define B_AX_DLE_WDE_STATE_V1_MASK GENMASK(31, 30)
2672 #define B_AX_TXRPT_CS_MASK GENMASK(4, 0)
2706 #define B_AX_PLE_WD_OPT_FSM_HANG_MSK BIT(4)
2764 #define B_AX_TX_RU0_FSM_HANG_ERR_MSK BIT(31)
2805 #define B_AX_TCR_ZLD_NUM_MASK GENMASK(31, 24)
2815 #define B_AX_TCR_EN_EOF BIT(4)
2823 #define B_AX_TXDFIFO_THRESHOLD GENMASK(31, 28)
2836 #define B_AX_TSFT_OFS_MASK GENMASK(31, 16)
2852 #define B_AX_HIGH_MCS_PHY_RATE_MASK GENMASK(7, 4)
2857 #define B_AX_MACTX_MPDU_CNT GENMASK(31, 24)
2871 #define B_AX_TX_CTRL_INFO_P0_MASK GENMASK(31, 0)
2875 #define B_AX_TX_CTRL_INFO_P1_MASK GENMASK(31, 0)
2892 #define B_AX_WMAC_RESP_STBC_EN BIT(31)
2914 #define B_AX_RESP_TX_MACID_CCA_TH_EN BIT(31)
2943 #define B_AX_RXTRIG_MACID_MASK GENMASK(31, 24)
2958 #define B_AX_TMAC_HWSIGB_GEN BIT(4)
2987 #define B_AX_HWSIGB_GEN_ERROR_FLAG_CLR BIT(4)
2999 #define B_AX_WMAC_TX_TF_INFO_P0_MASK GENMASK(31, 0)
3003 #define B_AX_WMAC_TX_TF_INFO_P1_MASK GENMASK(31, 0)
3038 #define B_AX_STS_ON_TIMEOUT_EN BIT(4)
3083 #define B_AX_BFMER_HE_CSI_OFFSET_MASK GENMASK(31, 24)
3091 #define B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK GENMASK(31, 24)
3149 #define B_AX_RX_DLK_DATA_TIME_MASK GENMASK(7, 4)
3156 #define B_AX_VHT_SU_SIGB_CRC_CHK BIT(4)
3164 #define B_AX_UID_FILTER_MASK GENMASK(31, 24)
3178 #define B_AX_A_UC_CAM_MATCH BIT(4)
3219 #define B_AX_PPDU_STAT_RPT_A1M BIT(4)
3236 #define B_AX_RX_STATE_MONITOR_MASK GENMASK(31, 0)
3237 #define B_AX_STATE_CUR_MASK GENMASK(31, 16)
3240 #define B_AX_STATE_SEL_MASK GENMASK(4, 0)
3244 #define B_AX_RXERR_INTPS_EN BIT(31)
3256 #define B_AX_BMAC_DATA_ON_TIMEOUT_FLAG BIT(4)
3281 #define B_AX_DATAON_ASSERT_TO_MSK BIT(4)
3309 #define B_AX_RMAC_PLCP_MON_MASK GENMASK(31, 0)
3310 #define B_AX_PCLP_MON_SEL_MASK GENMASK(31, 28)
3359 #define B_AX_PWR_UL_TB_CTRL_EN BIT(31)
3361 #define B_AX_PWR_UL_TB_1T_MASK GENMASK(4, 0)
3364 #define B_AX_PWR_UL_TB_2T_MASK GENMASK(4, 0)
3430 #define B_AX_BANDEDGE_CFG_IDX_MASK GENMASK(31, 30)
3439 #define B_AX_BTC_EN BIT(31)
3450 #define B_AX_BTC_DBG_SEL_MASK GENMASK(4, 3)
3505 #define MAC_AX_CSR_TRX_TO 4
3506 #define B_AX_BT_PRI_DETECT_TO_MASK GENMASK(7, 4)
3516 #define B_AX_STATIS_BT_HI_RX_MASK GENMASK(31, 16)
3520 #define B_AX_STATIS_BT_LO_RX_1_MASK GENMASK(31, 16)
3541 #define B_AX_GNT_BT_RFC_S0_SWCTRL BIT(4)
3549 #define B_AX_GNT_WL_RFC_S1_STA BIT(4)
3554 #define B_AX_GNT_BT_RFC_S1 BIT(4)
3561 #define B_AX_R_BT_CMD_RPT_MASK GENMASK(31, 16)
3565 #define B_AX_ENABLE_TDMA_FW_MODE BIT(4)
3573 #define B_AX_BT_TIME_MASK GENMASK(31, 6)
3590 #define B_AX_GNT_BT_RFC_S1_SW_VAL BIT(31)
3612 #define B_AX_LTECOEX_OP_MODE_SEL_MASK GENMASK(5, 4)
3622 #define B_AX_GNT_WL_TX_SW_CTRL BIT(4)
3632 #define B_BE_UID_FILTER_MASK GENMASK(31, 24)
3643 #define B_BE_A_UC_CAM_MATCH BIT(4)
3651 #define RR_MOD_IQK GENMASK(19, 4)
3655 #define RR_MOD_RGM GENMASK(13, 4)
3667 #define RR_MOD_M_RXG GENMASK(13, 4)
3682 #define RR_LOKVB_COQ GENMASK(9, 4)
3685 #define RR_TXIG_GR1 GENMASK(6, 4)
3711 #define RR_APK_MOD GENMASK(5, 4)
3733 #define RR_LUTWA_M2 GENMASK(4, 0)
3751 #define RR_TXGA_LOK_EXT GENMASK(4, 0)
3758 #define RR_GAINTX_BB GENMASK(4, 0)
3777 #define RR_BIASA2_LB GENMASK(4, 2)
3799 #define RR_RXBB_ATTR GENMASK(7, 4)
3816 #define RR_RXA2_IATT GENMASK(7, 4)
3855 #define RR_MIXER_GN GENMASK(4, 3)
3862 #define RR_IBD_VAL GENMASK(4, 0)
3880 #define RR_LCK_ST BIT(4)
3887 #define RR_SYNLUT_MOD BIT(4)
3910 #define B_UPD_P0_EN BIT(31)
3912 #define B_ANAPAR_PW15 GENMASK(31, 24)
3916 #define B_ANAPAR_15 GENMASK(31, 16)
3933 #define B_SWSI_DATA_BIT_MASK_EN_V1 BIT(31)
3981 #define B_PMAC_RXMOD_MSK GENMASK(7, 4)
3983 #define B_MAC_SEL_OFDM_TRI_FILTER BIT(31)
3986 #define B_MAC_SEL_MOD GENMASK(4, 2)
3990 #define B_PMAC_TX_PRD_MSK GENMASK(31, 8)
3992 #define B_PMAC_PTX_EN BIT(4)
3994 #define B_PMAC_TX_CNT_MSK GENMASK(31, 0)
4000 #define B_CCX_EDCCA_OPT_MSK GENMASK(6, 4)
4001 #define B_CCX_EDCCA_OPT_MSK_V1 GENMASK(7, 4)
4006 #define B_IFS_CLM_PERIOD_MSK GENMASK(31, 16)
4011 #define B_IFS_T1_TH_HIGH_MSK GENMASK(31, 16)
4015 #define B_IFS_T2_TH_HIGH_MSK GENMASK(31, 16)
4019 #define B_IFS_T3_TH_HIGH_MSK GENMASK(31, 16)
4023 #define B_IFS_T4_TH_HIGH_MSK GENMASK(31, 16)
4033 #define B_PD_ARBITER_OFF BIT(31)
4059 #define B_P0_RXCK_ADJ GENMASK(31, 23)
4067 #define B_P0_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)
4068 #define B_P0_RFMODE_MUX GENMASK(11, 4)
4077 #define B_S0_RXDC_Q GENMASK(31, 26)
4081 #define B_S0_RXDC2_MEN GENMASK(5, 4)
4094 #define B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK GENMASK(31, 16)
4098 #define B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK GENMASK(31, 16)
4102 #define B_IFS_CLM_OFDM_FA_MSK GENMASK(31, 16)
4106 #define B_IFS_T4_HIS_MSK GENMASK(31, 24)
4112 #define B_IFS_T2_AVG_MSK GENMASK(31, 16)
4116 #define B_IFS_T4_AVG_MSK GENMASK(31, 16)
4120 #define B_IFS_T2_CCA_MSK GENMASK(31, 16)
4124 #define B_IFS_T4_CCA_MSK GENMASK(31, 16)
4138 #define B_TXAGC_BTP GENMASK(31, 24)
4140 #define B_TXAGC_BB_OFT GENMASK(31, 16)
4141 #define B_TXAGC_BB GENMASK(31, 24)
4149 #define B_ADC_FIFO_RST GENMASK(31, 24)
4150 #define B_ADC_FIFO_RXK GENMASK(31, 16)
4176 #define B_RXCCA_DIS BIT(31)
4202 #define B_P1_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)
4203 #define B_P1_RFMODE_MUX GENMASK(11, 4)
4212 #define B_S1_RXDC_Q GENMASK(31, 26)
4214 #define B_S1_RXDC2_EN GENMASK(5, 4)
4218 #define B_TXAGC_BB_S1_OFT GENMASK(31, 16)
4219 #define B_TXAGC_BB_S1 GENMASK(31, 24)
4247 #define B_BT_DYN_DC_EST_EN_MSK BIT(31)
4249 #define B_ASSIGN_SBD_OPT_EN_V1 BIT(31)
4265 #define B_TXPATH_SEL_MSK GENMASK(31, 28)
4311 #define B_PATH0_TIA_ERR_G1_SEL GENMASK(31, 30)
4336 #define B_PATH0_G_LNA6_OP1DB_V1 GENMASK(31, 24)
4354 #define B_P0_BACKOFF_IBADC_V1 GENMASK(31, 26)
4357 #define B_P1_MODE_SEL GENMASK(31, 30)
4359 #define B_P0_AGC_EN BIT(31)
4372 #define B_PATH1_G_LNA6_OP1DB_V1 GENMASK(31, 24)
4401 #define B_SEG0R_PPDU_LVL_MSK GENMASK(31, 24)
4411 #define B_FC0_BW_SET GENMASK(31, 30)
4423 #define B_P0_RPL1_41_MASK GENMASK(31, 24)
4430 #define B_P0_RTL2_8A_MASK GENMASK(31, 24)
4435 #define B_P0_RTL3_89_MASK GENMASK(31, 24)
4442 #define B_P1_BACKOFF_IBADC_V1 GENMASK(31, 26)
4453 #define B_P1_AGC_EN BIT(31)
4458 #define B_PATH0_RXBB_MSK_V1 GENMASK(31, 0)
4461 #define B_PATH1_RXBB_MSK_V1 GENMASK(31, 0)
4518 #define B_BMODE_PDTH_LOWER_BOUND_MSK_V1 GENMASK(31, 24)
4543 #define B_DAC_VAL BIT(31)
4559 #define B_DPD_OFT_ADDR GENMASK(31, 27)
4574 #define B_P0_TSSI_EN BIT(31)
4596 #define B_P0_ANTSEL_RX_ORI GENMASK(7, 4)
4608 #define B_P0_RFM_OUT GENMASK(4, 0)
4611 #define B_P0_TXDPD GENMASK(31, 28)
4614 #define B_P0_TXPW_RSTB_TSSI BIT(31)
4621 #define B_TXGAIN_SCALE_OFT GENMASK(31, 24)
4624 #define B_S0_DACKI_AR GENMASK(31, 28)
4633 #define B_S0_DACKQ_AR GENMASK(31, 28)
4664 #define B_P1_TSSI_EN BIT(31)
4673 #define B_P1_TXPW_RSTB_TSSI BIT(31)
4680 #define B_S1_DACKI_AR GENMASK(31, 28)
4689 #define B_S1_DACKQ_AR GENMASK(31, 28)
4716 #define B_IQK_CFG_SET GENMASK(5, 4)
4723 #define B_MDPK_SYNC_SEL BIT(31)
4724 #define B_MDPK_SYNC_MAN GENMASK(31, 28)
4727 #define B_MDPK_RX_DCK_EN BIT(31)
4754 #define B_IDL_DN BIT(31)
4767 #define B_DPK_TRK_DIS BIT(31)
4775 #define B_PRT_COM_GL GENMASK(7, 4)
4778 #define B_PRT_COM_RXBB_V1 GENMASK(4, 0)
4793 #define B_RXIQC_NEWX GENMASK(31, 20)
4798 #define B_RFGAIN_PAD GENMASK(4, 0)
4801 #define B_RFGAIN_BND GENMASK(4, 0)
4805 #define B_CFIR_LUT_SET BIT(4)
4820 #define B_DPD_MEN GENMASK(31, 28)
4841 #define B_DPK_GL_A0 GENMASK(31, 28)
4844 #define B_RPT_PER_KSET GENMASK(31, 29)
4868 #define B_IQKINF_VER GENMASK(31, 24)
4878 #define B_IQKCH_BW GENMASK(7, 4)
4886 #define B_DCOF0_V GENMASK(4, 1)
4891 #define B_DCOF8_V GENMASK(4, 1)
4895 #define B_DACK_S0P0_OK BIT(31)
4899 #define B_DACK_S0M0 GENMASK(31, 24)
4902 #define B_DACK_DADCK00 GENMASK(31, 24)
4904 #define B_DACK_S0P1_OK BIT(31)
4908 #define B_DACK_S0M1 GENMASK(31, 24)
4911 #define B_DACK_DADCK01 GENMASK(31, 24)
4918 #define B_DRCK_VAL GENMASK(4, 0)
4925 #define B_DRCK_V1_CV GENMASK(4, 0)
4939 #define B_WDADC_SEL GENMASK(5, 4)
4941 #define B_ADCMOD_LP GENMASK(31, 16)
4945 #define B_ADDCK0D_VAL2 GENMASK(31, 26)
4952 #define B_ADDCK0_MAN GENMASK(5, 4)
4953 #define B_ADDCK0_EN BIT(4)
4962 #define B_ADDCKR0_DC GENMASK(15, 4)
4965 #define B_DACK10 GENMASK(4, 1)
4969 #define B_DACK11 GENMASK(4, 1)
4971 #define B_DACK_S1P0_OK BIT(31)
4975 #define B_DACK10S GENMASK(31, 24)
4979 #define B_DACK_DADCK10 GENMASK(31, 24)
4981 #define B_DACK_S1P1_OK BIT(31)
4985 #define B_DACK11S GENMASK(31, 24)
4989 #define B_DACK_DADCK11 GENMASK(31, 24)
4998 #define B_ADDCK1D_VAL2 GENMASK(31, 26)
5003 #define B_ADDCK1_MAN GENMASK(5, 4)
5004 #define B_ADDCK1_EN BIT(4)
5021 #define B_AX_WDT_EN BIT(31)