Lines Matching refs:rtw89_write32_set
183 rtw89_write32_set(rtwdev, dma_stop1->addr, dma_stop1->mask); in rtw89_pci_ctrl_txdma_ch_pcie()
185 rtw89_write32_set(rtwdev, dma_stop2->addr, dma_stop2->mask); in rtw89_pci_ctrl_txdma_ch_pcie()
197 rtw89_write32_set(rtwdev, dma_stop1->addr, B_AX_STOP_CH12); in rtw89_pci_ctrl_txdma_fw_ch_pcie()
1679 rtw89_write32_set(rtwdev, info->init_cfg_reg, in rtw89_pci_ctrl_dma_trx()
1702 rtw89_write32_set(rtwdev, reg, mask); in rtw89_pci_ctrl_dma_io()
2108 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_DIS_RXDMA_PRE); in rtw89_pci_rxdma_prefth()
2156 rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL, in rtw89_pci_hci_ldo()
2180 rtw89_write32_set(rtwdev, R_AX_HCI_OPT_CTRL, BIT_WAKE_CTRL); in rtw89_pci_power_wake()
2190 rtw89_write32_set(rtwdev, R_AX_PCIE_BG_CLR, B_AX_BG_CLR_ASYNC_M3); in rtw89_pci_autoload_hang()
2199 rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_FORCE_PWR_NGAT); in rtw89_pci_l12_vmain()
2207 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, in rtw89_pci_gen2_force_ib()
2209 rtw89_write32_set(rtwdev, R_AX_HCI_BG_CTRL, B_AX_BG_CLR_ASYNC_M3); in rtw89_pci_gen2_force_ib()
2227 rtw89_write32_set(rtwdev, R_AX_PCIE_PS_CTRL_V1, B_AX_DMAC0_EXIT_L1_EN); in rtw89_pci_wd_exit_l1()
2255 rtw89_write32_set(rtwdev, R_AX_LBC_WATCHDOG, lbc); in rtw89_pci_set_lbc()
2273 rtw89_write32_set(rtwdev, R_AX_PCIE_IO_RCY_M1, B_AX_PCIE_IO_RCY_WDT_MODE_M1); in rtw89_pci_set_io_rcy()
2274 rtw89_write32_set(rtwdev, R_AX_PCIE_IO_RCY_M2, B_AX_PCIE_IO_RCY_WDT_MODE_M2); in rtw89_pci_set_io_rcy()
2275 rtw89_write32_set(rtwdev, R_AX_PCIE_IO_RCY_E0, B_AX_PCIE_IO_RCY_WDT_MODE_E0); in rtw89_pci_set_io_rcy()
2290 rtw89_write32_set(rtwdev, R_AX_PCIE_DBG_CTRL, in rtw89_pci_set_dbg()
2294 rtw89_write32_set(rtwdev, R_AX_PCIE_EXP_CTRL, in rtw89_pci_set_dbg()
2303 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, in rtw89_pci_set_keep_reg()
2321 rtw89_write32_set(rtwdev, R_AX_TXBD_RWPTR_CLR1, val); in rtw89_pci_clr_idx_all()
2323 rtw89_write32_set(rtwdev, txbd_rwptr_clr2, in rtw89_pci_clr_idx_all()
2325 rtw89_write32_set(rtwdev, rxbd_rwptr_clr, in rtw89_pci_clr_idx_all()
2408 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_TX_TRUNC_MODE); in rtw89_pci_mode_op()
2416 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_RX_TRUNC_MODE); in rtw89_pci_mode_op()
2425 rtw89_write32_set(rtwdev, info->init_cfg_reg, info->rxbd_mode_bit); in rtw89_pci_mode_op()
2468 rtw89_write32_set(rtwdev, R_AX_TX_ADDRESS_INFO_MODE_SETTING, in rtw89_pci_mode_op()
2474 rtw89_write32_set(rtwdev, R_AX_PKTIN_SETTING, B_AX_WD_ADDR_INFO_LENGTH); in rtw89_pci_mode_op()
2486 rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_APP_LTR_IDLE); in rtw89_pci_ops_deinit()
2537 rtw89_write32_set(rtwdev, info->dma_stop1.addr, B_AX_STOP_WPDMA); in rtw89_pci_ops_mac_pre_init()
2590 rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_HW_EN | B_AX_LTR_EN | in rtw89_pci_ltr_set()
2638 rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, in rtw89_pci_ltr_set_v1()
2665 rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_APP_LTR_ACT); in rtw89_pci_ops_mac_post_init()
2669 rtw89_write32_set(rtwdev, R_AX_TX_ADDRESS_INFO_MODE_SETTING, in rtw89_pci_ops_mac_post_init()
3428 rtw89_write32_set(rtwdev, R_AX_PCIE_LAT_CTRL, in rtw89_pci_clkreq_set()
3431 rtw89_write32_set(rtwdev, R_AX_L1_CLK_CTRL, in rtw89_pci_clkreq_set()
3471 rtw89_write32_set(rtwdev, R_AX_PCIE_MIX_CFG_V1, in rtw89_pci_aspm_set()
3562 rtw89_write32_set(rtwdev, R_AX_PCIE_MIX_CFG_V1, in rtw89_pci_l1ss_set()
3641 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, val32); in rtw89_pci_rst_bdram()
3736 rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); in rtw89_pci_suspend()
3737 rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST); in rtw89_pci_suspend()
3742 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, in rtw89_pci_suspend()
3770 rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); in rtw89_pci_resume()
3774 rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL, in rtw89_pci_resume()
3779 rtw89_write32_set(rtwdev, R_AX_PCIE_PS_CTRL_V1, in rtw89_pci_resume()