Lines Matching refs:rtwdev
39 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, in rtw89_mac_mem_write() argument
42 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; in rtw89_mac_mem_write()
45 rtw89_write32(rtwdev, mac->filter_model_addr, addr); in rtw89_mac_mem_write()
46 rtw89_write32(rtwdev, mac->indir_access_addr, val); in rtw89_mac_mem_write()
49 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, in rtw89_mac_mem_read() argument
52 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; in rtw89_mac_mem_read()
55 rtw89_write32(rtwdev, mac->filter_model_addr, addr); in rtw89_mac_mem_read()
56 return rtw89_read32(rtwdev, mac->indir_access_addr); in rtw89_mac_mem_read()
59 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx, in rtw89_mac_check_mac_en() argument
65 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); in rtw89_mac_check_mac_en()
68 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); in rtw89_mac_check_mac_en()
71 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); in rtw89_mac_check_mac_en()
83 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) in rtw89_mac_write_lte() argument
89 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); in rtw89_mac_write_lte()
91 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); in rtw89_mac_write_lte()
93 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); in rtw89_mac_write_lte()
94 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); in rtw89_mac_write_lte()
99 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) in rtw89_mac_read_lte() argument
105 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); in rtw89_mac_read_lte()
107 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); in rtw89_mac_read_lte()
109 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); in rtw89_mac_read_lte()
110 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); in rtw89_mac_read_lte()
116 int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) in dle_dfi_ctrl() argument
138 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); in dle_dfi_ctrl()
142 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); in dle_dfi_ctrl()
145 1, 1000, false, rtwdev, ctrl_reg); in dle_dfi_ctrl()
147 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", in dle_dfi_ctrl()
152 ctrl->out_data = rtw89_read32(rtwdev, data_reg); in dle_dfi_ctrl()
156 static int dle_dfi_quota(struct rtw89_dev *rtwdev, in dle_dfi_quota() argument
165 ret = dle_dfi_ctrl(rtwdev, &ctrl); in dle_dfi_quota()
167 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); in dle_dfi_quota()
176 static int dle_dfi_qempty(struct rtw89_dev *rtwdev, in dle_dfi_qempty() argument
185 ret = dle_dfi_ctrl(rtwdev, &ctrl); in dle_dfi_qempty()
187 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); in dle_dfi_qempty()
195 static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev) in dump_err_status_dispatcher() argument
197 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", in dump_err_status_dispatcher()
198 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); in dump_err_status_dispatcher()
199 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", in dump_err_status_dispatcher()
200 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); in dump_err_status_dispatcher()
201 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", in dump_err_status_dispatcher()
202 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); in dump_err_status_dispatcher()
203 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", in dump_err_status_dispatcher()
204 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); in dump_err_status_dispatcher()
205 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", in dump_err_status_dispatcher()
206 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); in dump_err_status_dispatcher()
207 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", in dump_err_status_dispatcher()
208 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); in dump_err_status_dispatcher()
211 static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev) in rtw89_mac_dump_qta_lost() argument
222 ret = dle_dfi_qempty(rtwdev, &qempty); in rtw89_mac_dump_qta_lost()
224 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); in rtw89_mac_dump_qta_lost()
226 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); in rtw89_mac_dump_qta_lost()
235 ret = dle_dfi_ctrl(rtwdev, &ctrl); in rtw89_mac_dump_qta_lost()
237 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); in rtw89_mac_dump_qta_lost()
239 rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i, in rtw89_mac_dump_qta_lost()
246 ret = dle_dfi_quota(rtwdev, "a); in rtw89_mac_dump_qta_lost()
248 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); in rtw89_mac_dump_qta_lost()
250 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", in rtw89_mac_dump_qta_lost()
253 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); in rtw89_mac_dump_qta_lost()
254 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n", in rtw89_mac_dump_qta_lost()
256 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n", in rtw89_mac_dump_qta_lost()
259 dump_err_status_dispatcher(rtwdev); in rtw89_mac_dump_qta_lost()
262 static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, in rtw89_mac_dump_l0_to_l1() argument
267 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); in rtw89_mac_dump_l0_to_l1()
272 rtw89_info(rtwdev, "quota lost!\n"); in rtw89_mac_dump_l0_to_l1()
273 rtw89_mac_dump_qta_lost(rtwdev); in rtw89_mac_dump_l0_to_l1()
280 static void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) in rtw89_mac_dump_dmac_err_status() argument
282 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_mac_dump_dmac_err_status()
286 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); in rtw89_mac_dump_dmac_err_status()
288 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); in rtw89_mac_dump_dmac_err_status()
292 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); in rtw89_mac_dump_dmac_err_status()
293 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); in rtw89_mac_dump_dmac_err_status()
294 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
295 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); in rtw89_mac_dump_dmac_err_status()
298 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
299 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); in rtw89_mac_dump_dmac_err_status()
300 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
301 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); in rtw89_mac_dump_dmac_err_status()
303 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
304 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); in rtw89_mac_dump_dmac_err_status()
305 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
306 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); in rtw89_mac_dump_dmac_err_status()
307 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
308 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); in rtw89_mac_dump_dmac_err_status()
309 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
310 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); in rtw89_mac_dump_dmac_err_status()
315 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
316 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); in rtw89_mac_dump_dmac_err_status()
317 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
318 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); in rtw89_mac_dump_dmac_err_status()
320 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
321 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); in rtw89_mac_dump_dmac_err_status()
323 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
324 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); in rtw89_mac_dump_dmac_err_status()
329 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
330 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); in rtw89_mac_dump_dmac_err_status()
331 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
332 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); in rtw89_mac_dump_dmac_err_status()
333 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
334 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); in rtw89_mac_dump_dmac_err_status()
335 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
336 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); in rtw89_mac_dump_dmac_err_status()
337 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
338 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); in rtw89_mac_dump_dmac_err_status()
339 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
340 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); in rtw89_mac_dump_dmac_err_status()
341 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
342 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); in rtw89_mac_dump_dmac_err_status()
343 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
344 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); in rtw89_mac_dump_dmac_err_status()
345 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
346 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); in rtw89_mac_dump_dmac_err_status()
348 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, in rtw89_mac_dump_dmac_err_status()
350 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, in rtw89_mac_dump_dmac_err_status()
352 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, in rtw89_mac_dump_dmac_err_status()
355 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, in rtw89_mac_dump_dmac_err_status()
357 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
358 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); in rtw89_mac_dump_dmac_err_status()
361 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
362 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); in rtw89_mac_dump_dmac_err_status()
363 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
364 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); in rtw89_mac_dump_dmac_err_status()
365 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
366 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); in rtw89_mac_dump_dmac_err_status()
367 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
368 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); in rtw89_mac_dump_dmac_err_status()
369 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
370 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); in rtw89_mac_dump_dmac_err_status()
371 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
372 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); in rtw89_mac_dump_dmac_err_status()
373 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
374 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); in rtw89_mac_dump_dmac_err_status()
375 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
376 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); in rtw89_mac_dump_dmac_err_status()
377 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
378 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); in rtw89_mac_dump_dmac_err_status()
379 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
380 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); in rtw89_mac_dump_dmac_err_status()
385 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
386 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); in rtw89_mac_dump_dmac_err_status()
387 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
388 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); in rtw89_mac_dump_dmac_err_status()
389 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
390 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); in rtw89_mac_dump_dmac_err_status()
391 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
392 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); in rtw89_mac_dump_dmac_err_status()
396 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
397 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); in rtw89_mac_dump_dmac_err_status()
398 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
399 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); in rtw89_mac_dump_dmac_err_status()
403 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
404 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); in rtw89_mac_dump_dmac_err_status()
405 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
406 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); in rtw89_mac_dump_dmac_err_status()
407 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
408 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); in rtw89_mac_dump_dmac_err_status()
409 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
410 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); in rtw89_mac_dump_dmac_err_status()
415 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
416 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); in rtw89_mac_dump_dmac_err_status()
417 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
418 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); in rtw89_mac_dump_dmac_err_status()
419 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
420 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); in rtw89_mac_dump_dmac_err_status()
421 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
422 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); in rtw89_mac_dump_dmac_err_status()
424 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
425 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); in rtw89_mac_dump_dmac_err_status()
426 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
427 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); in rtw89_mac_dump_dmac_err_status()
432 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
433 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); in rtw89_mac_dump_dmac_err_status()
434 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
435 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); in rtw89_mac_dump_dmac_err_status()
436 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
437 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); in rtw89_mac_dump_dmac_err_status()
438 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
439 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); in rtw89_mac_dump_dmac_err_status()
440 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
441 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); in rtw89_mac_dump_dmac_err_status()
442 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
443 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); in rtw89_mac_dump_dmac_err_status()
444 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
445 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); in rtw89_mac_dump_dmac_err_status()
446 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
447 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); in rtw89_mac_dump_dmac_err_status()
448 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
449 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); in rtw89_mac_dump_dmac_err_status()
450 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
451 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); in rtw89_mac_dump_dmac_err_status()
452 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
453 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); in rtw89_mac_dump_dmac_err_status()
454 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
455 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); in rtw89_mac_dump_dmac_err_status()
457 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
458 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); in rtw89_mac_dump_dmac_err_status()
459 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
460 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); in rtw89_mac_dump_dmac_err_status()
461 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
462 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); in rtw89_mac_dump_dmac_err_status()
464 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
465 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); in rtw89_mac_dump_dmac_err_status()
466 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
467 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); in rtw89_mac_dump_dmac_err_status()
468 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
469 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); in rtw89_mac_dump_dmac_err_status()
474 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
475 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); in rtw89_mac_dump_dmac_err_status()
476 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
477 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); in rtw89_mac_dump_dmac_err_status()
481 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
482 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); in rtw89_mac_dump_dmac_err_status()
483 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
484 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); in rtw89_mac_dump_dmac_err_status()
485 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
486 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); in rtw89_mac_dump_dmac_err_status()
487 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
488 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); in rtw89_mac_dump_dmac_err_status()
489 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
490 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); in rtw89_mac_dump_dmac_err_status()
491 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
492 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); in rtw89_mac_dump_dmac_err_status()
497 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
498 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); in rtw89_mac_dump_dmac_err_status()
499 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
500 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); in rtw89_mac_dump_dmac_err_status()
501 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
502 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); in rtw89_mac_dump_dmac_err_status()
503 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
504 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); in rtw89_mac_dump_dmac_err_status()
505 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
506 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); in rtw89_mac_dump_dmac_err_status()
507 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
508 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); in rtw89_mac_dump_dmac_err_status()
510 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
511 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); in rtw89_mac_dump_dmac_err_status()
512 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
513 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); in rtw89_mac_dump_dmac_err_status()
514 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
515 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); in rtw89_mac_dump_dmac_err_status()
516 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
517 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); in rtw89_mac_dump_dmac_err_status()
518 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
519 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); in rtw89_mac_dump_dmac_err_status()
524 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
525 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); in rtw89_mac_dump_dmac_err_status()
526 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", in rtw89_mac_dump_dmac_err_status()
527 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); in rtw89_mac_dump_dmac_err_status()
531 static void rtw89_mac_dump_cmac_err_status(struct rtw89_dev *rtwdev, in rtw89_mac_dump_cmac_err_status() argument
534 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_mac_dump_cmac_err_status()
539 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); in rtw89_mac_dump_cmac_err_status()
542 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); in rtw89_mac_dump_cmac_err_status()
544 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); in rtw89_mac_dump_cmac_err_status()
551 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); in rtw89_mac_dump_cmac_err_status()
552 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, in rtw89_mac_dump_cmac_err_status()
553 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); in rtw89_mac_dump_cmac_err_status()
554 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, in rtw89_mac_dump_cmac_err_status()
555 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); in rtw89_mac_dump_cmac_err_status()
556 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, in rtw89_mac_dump_cmac_err_status()
557 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); in rtw89_mac_dump_cmac_err_status()
560 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, in rtw89_mac_dump_cmac_err_status()
561 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); in rtw89_mac_dump_cmac_err_status()
562 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, in rtw89_mac_dump_cmac_err_status()
563 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); in rtw89_mac_dump_cmac_err_status()
567 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, in rtw89_mac_dump_cmac_err_status()
568 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); in rtw89_mac_dump_cmac_err_status()
569 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, in rtw89_mac_dump_cmac_err_status()
570 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); in rtw89_mac_dump_cmac_err_status()
575 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, in rtw89_mac_dump_cmac_err_status()
576 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); in rtw89_mac_dump_cmac_err_status()
577 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, in rtw89_mac_dump_cmac_err_status()
578 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); in rtw89_mac_dump_cmac_err_status()
580 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, in rtw89_mac_dump_cmac_err_status()
581 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); in rtw89_mac_dump_cmac_err_status()
587 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, in rtw89_mac_dump_cmac_err_status()
588 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); in rtw89_mac_dump_cmac_err_status()
589 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, in rtw89_mac_dump_cmac_err_status()
590 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); in rtw89_mac_dump_cmac_err_status()
592 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, in rtw89_mac_dump_cmac_err_status()
593 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); in rtw89_mac_dump_cmac_err_status()
598 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, in rtw89_mac_dump_cmac_err_status()
599 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); in rtw89_mac_dump_cmac_err_status()
600 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, in rtw89_mac_dump_cmac_err_status()
601 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); in rtw89_mac_dump_cmac_err_status()
606 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, in rtw89_mac_dump_cmac_err_status()
607 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); in rtw89_mac_dump_cmac_err_status()
608 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, in rtw89_mac_dump_cmac_err_status()
609 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); in rtw89_mac_dump_cmac_err_status()
611 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, in rtw89_mac_dump_cmac_err_status()
612 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); in rtw89_mac_dump_cmac_err_status()
614 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, in rtw89_mac_dump_cmac_err_status()
615 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); in rtw89_mac_dump_cmac_err_status()
618 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, in rtw89_mac_dump_cmac_err_status()
619 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); in rtw89_mac_dump_cmac_err_status()
622 static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev, in rtw89_mac_dump_err_status() argument
632 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); in rtw89_mac_dump_err_status()
633 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", in rtw89_mac_dump_err_status()
634 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); in rtw89_mac_dump_err_status()
636 rtw89_mac_dump_dmac_err_status(rtwdev); in rtw89_mac_dump_err_status()
637 rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_0); in rtw89_mac_dump_err_status()
638 if (rtwdev->dbcc_en) in rtw89_mac_dump_err_status()
639 rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_1); in rtw89_mac_dump_err_status()
641 rtwdev->hci.ops->dump_err_status(rtwdev); in rtw89_mac_dump_err_status()
644 rtw89_mac_dump_l0_to_l1(rtwdev, err); in rtw89_mac_dump_err_status()
646 rtw89_info(rtwdev, "<---\n"); in rtw89_mac_dump_err_status()
649 static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err) in rtw89_mac_suppress_log() argument
651 struct rtw89_ser *ser = &rtwdev->ser; in rtw89_mac_suppress_log()
655 if (rtwdev->chip->chip_id == RTL8852C) { in rtw89_mac_suppress_log()
656 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); in rtw89_mac_suppress_log()
661 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); in rtw89_mac_suppress_log()
662 imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR); in rtw89_mac_suppress_log()
663 isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR); in rtw89_mac_suppress_log()
682 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) in rtw89_mac_get_err_status() argument
688 false, rtwdev, R_AX_HALT_C2H_CTRL); in rtw89_mac_get_err_status()
690 rtw89_warn(rtwdev, "Polling FW err status fail\n"); in rtw89_mac_get_err_status()
694 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); in rtw89_mac_get_err_status()
695 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); in rtw89_mac_get_err_status()
705 if (rtw89_mac_suppress_log(rtwdev, err)) in rtw89_mac_get_err_status()
708 rtw89_fw_st_dbg_dump(rtwdev); in rtw89_mac_get_err_status()
709 rtw89_mac_dump_err_status(rtwdev, err); in rtw89_mac_get_err_status()
715 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) in rtw89_mac_set_err_status() argument
717 struct rtw89_ser *ser = &rtwdev->ser; in rtw89_mac_set_err_status()
722 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); in rtw89_mac_set_err_status()
727 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); in rtw89_mac_set_err_status()
729 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); in rtw89_mac_set_err_status()
733 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); in rtw89_mac_set_err_status()
739 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); in rtw89_mac_set_err_status()
745 static int hfc_reset_param(struct rtw89_dev *rtwdev) in hfc_reset_param() argument
747 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_reset_param()
749 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; in hfc_reset_param()
751 switch (rtwdev->hci.type) { in hfc_reset_param()
753 param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; in hfc_reset_param()
776 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) in hfc_ch_cfg_chk() argument
778 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_ch_cfg_chk()
795 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) in hfc_pub_info_chk() argument
797 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_pub_info_chk()
802 if (rtwdev->chip->chip_id == RTL8852A) in hfc_pub_info_chk()
811 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) in hfc_pub_cfg_chk() argument
813 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_pub_cfg_chk()
822 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) in hfc_ch_ctrl() argument
824 const struct rtw89_chip_info *chip = rtwdev->chip; in hfc_ch_ctrl()
826 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_ch_ctrl()
831 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); in hfc_ch_ctrl()
835 ret = hfc_ch_cfg_chk(rtwdev, ch); in hfc_ch_ctrl()
845 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); in hfc_ch_ctrl()
850 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) in hfc_upd_ch_info() argument
852 const struct rtw89_chip_info *chip = rtwdev->chip; in hfc_upd_ch_info()
854 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_upd_ch_info()
860 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); in hfc_upd_ch_info()
867 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); in hfc_upd_ch_info()
877 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) in hfc_pub_ctrl() argument
879 const struct rtw89_chip_info *chip = rtwdev->chip; in hfc_pub_ctrl()
881 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; in hfc_pub_ctrl()
885 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); in hfc_pub_ctrl()
889 ret = hfc_pub_cfg_chk(rtwdev); in hfc_pub_ctrl()
895 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); in hfc_pub_ctrl()
898 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); in hfc_pub_ctrl()
903 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) in hfc_upd_mix_info() argument
905 const struct rtw89_chip_info *chip = rtwdev->chip; in hfc_upd_mix_info()
907 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_upd_mix_info()
914 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); in hfc_upd_mix_info()
918 val = rtw89_read32(rtwdev, regs->pub_page_info1); in hfc_upd_mix_info()
921 val = rtw89_read32(rtwdev, regs->pub_page_info3); in hfc_upd_mix_info()
925 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), in hfc_upd_mix_info()
928 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), in hfc_upd_mix_info()
931 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); in hfc_upd_mix_info()
944 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); in hfc_upd_mix_info()
948 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); in hfc_upd_mix_info()
951 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); in hfc_upd_mix_info()
955 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); in hfc_upd_mix_info()
958 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); in hfc_upd_mix_info()
962 ret = hfc_pub_info_chk(rtwdev); in hfc_upd_mix_info()
969 static void hfc_h2c_cfg(struct rtw89_dev *rtwdev) in hfc_h2c_cfg() argument
971 const struct rtw89_chip_info *chip = rtwdev->chip; in hfc_h2c_cfg()
973 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_h2c_cfg()
978 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); in hfc_h2c_cfg()
980 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, in hfc_h2c_cfg()
985 static void hfc_mix_cfg(struct rtw89_dev *rtwdev) in hfc_mix_cfg() argument
987 const struct rtw89_chip_info *chip = rtwdev->chip; in hfc_mix_cfg()
989 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_mix_cfg()
996 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); in hfc_mix_cfg()
999 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); in hfc_mix_cfg()
1005 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); in hfc_mix_cfg()
1007 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), in hfc_mix_cfg()
1017 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); in hfc_mix_cfg()
1020 static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en) in hfc_func_en() argument
1022 const struct rtw89_chip_info *chip = rtwdev->chip; in hfc_func_en()
1024 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_func_en()
1027 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); in hfc_func_en()
1033 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); in hfc_func_en()
1036 static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) in hfc_init() argument
1038 const struct rtw89_chip_info *chip = rtwdev->chip; in hfc_init()
1044 ret = hfc_reset_param(rtwdev); in hfc_init()
1048 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); in hfc_init()
1052 hfc_func_en(rtwdev, false, false); in hfc_init()
1055 hfc_h2c_cfg(rtwdev); in hfc_init()
1056 hfc_func_en(rtwdev, en, h2c_en); in hfc_init()
1063 ret = hfc_ch_ctrl(rtwdev, ch); in hfc_init()
1068 ret = hfc_pub_ctrl(rtwdev); in hfc_init()
1072 hfc_mix_cfg(rtwdev); in hfc_init()
1074 hfc_func_en(rtwdev, en, h2c_en); in hfc_init()
1080 ret = hfc_upd_ch_info(rtwdev, ch); in hfc_init()
1084 ret = hfc_upd_mix_info(rtwdev); in hfc_init()
1090 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, in pwr_cmd_poll() argument
1099 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); in pwr_cmd_poll()
1104 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); in pwr_cmd_poll()
1105 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); in pwr_cmd_poll()
1106 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); in pwr_cmd_poll()
1111 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, in rtw89_mac_sub_pwr_seq() argument
1130 val = rtw89_read8(rtwdev, addr); in rtw89_mac_sub_pwr_seq()
1134 rtw89_write8(rtwdev, addr, val); in rtw89_mac_sub_pwr_seq()
1137 if (pwr_cmd_poll(rtwdev, cur_cfg)) in rtw89_mac_sub_pwr_seq()
1154 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, in rtw89_mac_pwr_seq() argument
1160 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), in rtw89_mac_pwr_seq()
1170 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) in rtw89_mac_get_req_pwr_state() argument
1174 switch (rtwdev->ps_mode) { in rtw89_mac_get_req_pwr_state()
1191 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, in rtw89_mac_send_rpwm() argument
1197 spin_lock_bh(&rtwdev->rpwm_lock); in rtw89_mac_send_rpwm()
1199 request = rtw89_read16(rtwdev, R_AX_RPWM); in rtw89_mac_send_rpwm()
1206 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & in rtw89_mac_send_rpwm()
1209 rtwdev->mac.rpwm_seq_num); in rtw89_mac_send_rpwm()
1214 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); in rtw89_mac_send_rpwm()
1216 spin_unlock_bh(&rtwdev->rpwm_lock); in rtw89_mac_send_rpwm()
1219 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, in rtw89_mac_check_cpwm_state() argument
1234 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) in rtw89_mac_check_cpwm_state()
1245 rpwm_req_num = rtwdev->mac.rpwm_seq_num; in rtw89_mac_check_cpwm_state()
1246 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, in rtw89_mac_check_cpwm_state()
1252 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & in rtw89_mac_check_cpwm_state()
1255 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); in rtw89_mac_check_cpwm_state()
1256 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) in rtw89_mac_check_cpwm_state()
1259 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); in rtw89_mac_check_cpwm_state()
1266 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) in rtw89_mac_power_mode_change() argument
1274 state = rtw89_mac_get_req_pwr_state(rtwdev); in rtw89_mac_power_mode_change()
1279 rtw89_mac_send_rpwm(rtwdev, state, false); in rtw89_mac_power_mode_change()
1282 rtwdev, state); in rtw89_mac_power_mode_change()
1287 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", in rtw89_mac_power_mode_change()
1290 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, in rtw89_mac_power_mode_change()
1296 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) in rtw89_mac_notify_wake() argument
1300 state = rtw89_mac_get_req_pwr_state(rtwdev); in rtw89_mac_notify_wake()
1301 rtw89_mac_send_rpwm(rtwdev, state, true); in rtw89_mac_notify_wake()
1304 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) in rtw89_mac_power_switch() argument
1307 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_mac_power_switch()
1309 int (*cfg_func)(struct rtw89_dev *rtwdev); in rtw89_mac_power_switch()
1321 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) in rtw89_mac_power_switch()
1322 __rtw89_leave_ps_mode(rtwdev); in rtw89_mac_power_switch()
1324 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); in rtw89_mac_power_switch()
1326 rtw89_err(rtwdev, "MAC has already powered on\n"); in rtw89_mac_power_switch()
1330 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); in rtw89_mac_power_switch()
1335 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); in rtw89_mac_power_switch()
1336 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); in rtw89_mac_power_switch()
1338 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); in rtw89_mac_power_switch()
1339 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); in rtw89_mac_power_switch()
1340 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); in rtw89_mac_power_switch()
1341 rtw89_set_entity_state(rtwdev, false); in rtw89_mac_power_switch()
1348 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) in rtw89_mac_pwr_off() argument
1350 rtw89_mac_power_switch(rtwdev, false); in rtw89_mac_pwr_off()
1353 static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) in cmac_func_en() argument
1376 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); in cmac_func_en()
1377 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, in cmac_func_en()
1379 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, in cmac_func_en()
1382 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); in cmac_func_en()
1383 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); in cmac_func_en()
1385 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); in cmac_func_en()
1386 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); in cmac_func_en()
1388 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, in cmac_func_en()
1390 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, in cmac_func_en()
1392 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); in cmac_func_en()
1399 static int dmac_func_en(struct rtw89_dev *rtwdev) in dmac_func_en() argument
1401 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; in dmac_func_en()
1420 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); in dmac_func_en()
1426 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); in dmac_func_en()
1431 static int chip_func_en(struct rtw89_dev *rtwdev) in chip_func_en() argument
1433 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; in chip_func_en()
1436 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, in chip_func_en()
1442 static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev) in rtw89_mac_sys_init() argument
1446 ret = dmac_func_en(rtwdev); in rtw89_mac_sys_init()
1450 ret = cmac_func_en(rtwdev, 0, true); in rtw89_mac_sys_init()
1454 ret = chip_func_en(rtwdev); in rtw89_mac_sys_init()
1528 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, in get_dle_mem_cfg() argument
1531 struct rtw89_mac_info *mac = &rtwdev->mac; in get_dle_mem_cfg()
1534 cfg = &rtwdev->chip->dle_mem[mode]; in get_dle_mem_cfg()
1539 rtw89_warn(rtwdev, "qta mode unmatch!\n"); in get_dle_mem_cfg()
1551 static bool mac_is_txq_empty(struct rtw89_dev *rtwdev) in mac_is_txq_empty() argument
1557 qnum = rtwdev->chip->wde_qempty_acq_num; in mac_is_txq_empty()
1562 ret = dle_dfi_qempty(rtwdev, &qempty); in mac_is_txq_empty()
1564 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); in mac_is_txq_empty()
1576 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_sel; in mac_is_txq_empty()
1577 ret = dle_dfi_qempty(rtwdev, &qempty); in mac_is_txq_empty()
1579 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); in mac_is_txq_empty()
1586 if (rtwdev->dbcc_en) { in mac_is_txq_empty()
1600 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); in mac_is_txq_empty()
1612 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, in dle_expected_used_size() argument
1615 u32 size = rtwdev->chip->fifo_size; in dle_expected_used_size()
1618 size -= rtwdev->chip->dle_scc_rsvd_size; in dle_expected_used_size()
1623 static void dle_func_en(struct rtw89_dev *rtwdev, bool enable) in dle_func_en() argument
1626 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, in dle_func_en()
1629 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, in dle_func_en()
1633 static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable) in dle_clk_en() argument
1638 if (rtwdev->chip->chip_id == RTL8851B) in dle_clk_en()
1640 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); in dle_clk_en()
1642 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); in dle_clk_en()
1646 static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) in dle_mix_cfg() argument
1652 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); in dle_mix_cfg()
1666 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); in dle_mix_cfg()
1673 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); in dle_mix_cfg()
1675 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); in dle_mix_cfg()
1683 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); in dle_mix_cfg()
1698 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); in dle_mix_cfg()
1708 rtw89_write32(rtwdev, \
1715 static void wde_quota_cfg(struct rtw89_dev *rtwdev, in wde_quota_cfg() argument
1730 static void ple_quota_cfg(struct rtw89_dev *rtwdev, in ple_quota_cfg() argument
1747 if (rtwdev->chip->chip_id == RTL8852C) in ple_quota_cfg()
1751 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) in rtw89_mac_resize_ple_rx_quota() argument
1757 if (rtwdev->chip->chip_id == RTL8852C) in rtw89_mac_resize_ple_rx_quota()
1760 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { in rtw89_mac_resize_ple_rx_quota()
1761 rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); in rtw89_mac_resize_ple_rx_quota()
1766 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); in rtw89_mac_resize_ple_rx_quota()
1768 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); in rtw89_mac_resize_ple_rx_quota()
1770 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); in rtw89_mac_resize_ple_rx_quota()
1783 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) in rtw89_mac_hw_mgnt_sec() argument
1788 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); in rtw89_mac_hw_mgnt_sec()
1790 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); in rtw89_mac_hw_mgnt_sec()
1793 static void dle_quota_cfg(struct rtw89_dev *rtwdev, in dle_quota_cfg() argument
1797 wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); in dle_quota_cfg()
1798 ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); in dle_quota_cfg()
1801 static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, in dle_init() argument
1809 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); in dle_init()
1813 cfg = get_dle_mem_cfg(rtwdev, mode); in dle_init()
1815 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); in dle_init()
1821 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); in dle_init()
1823 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", in dle_init()
1832 dle_expected_used_size(rtwdev, mode)) { in dle_init()
1833 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); in dle_init()
1838 dle_func_en(rtwdev, false); in dle_init()
1839 dle_clk_en(rtwdev, true); in dle_init()
1841 ret = dle_mix_cfg(rtwdev, cfg); in dle_init()
1843 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); in dle_init()
1846 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); in dle_init()
1848 dle_func_en(rtwdev, true); in dle_init()
1852 2000, false, rtwdev, R_AX_WDE_INI_STATUS); in dle_init()
1854 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); in dle_init()
1860 2000, false, rtwdev, R_AX_PLE_INI_STATUS); in dle_init()
1862 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); in dle_init()
1868 dle_func_en(rtwdev, false); in dle_init()
1869 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", in dle_init()
1870 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); in dle_init()
1871 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", in dle_init()
1872 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); in dle_init()
1877 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, in preload_init_set() argument
1886 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); in preload_init_set()
1887 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); in preload_init_set()
1892 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); in preload_init_set()
1893 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); in preload_init_set()
1898 static bool is_qta_poh(struct rtw89_dev *rtwdev) in is_qta_poh() argument
1900 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; in is_qta_poh()
1903 static int preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, in preload_init() argument
1906 const struct rtw89_chip_info *chip = rtwdev->chip; in preload_init()
1909 chip->chip_id == RTL8851B || !is_qta_poh(rtwdev)) in preload_init()
1912 return preload_init_set(rtwdev, mac_idx, mode); in preload_init()
1915 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) in dle_is_txq_empty() argument
1933 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); in dle_is_txq_empty()
1941 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) in _patch_ss2f_path() argument
1943 const struct rtw89_chip_info *chip = rtwdev->chip; in _patch_ss2f_path()
1949 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, in _patch_ss2f_path()
1953 static int sta_sch_init(struct rtw89_dev *rtwdev) in sta_sch_init() argument
1959 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); in sta_sch_init()
1963 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); in sta_sch_init()
1965 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); in sta_sch_init()
1968 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); in sta_sch_init()
1970 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); in sta_sch_init()
1974 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); in sta_sch_init()
1975 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); in sta_sch_init()
1977 _patch_ss2f_path(rtwdev); in sta_sch_init()
1982 static int mpdu_proc_init(struct rtw89_dev *rtwdev) in mpdu_proc_init() argument
1986 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); in mpdu_proc_init()
1990 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); in mpdu_proc_init()
1991 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); in mpdu_proc_init()
1992 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, in mpdu_proc_init()
1994 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); in mpdu_proc_init()
1999 static int sec_eng_init(struct rtw89_dev *rtwdev) in sec_eng_init() argument
2001 const struct rtw89_chip_info *chip = rtwdev->chip; in sec_eng_init()
2005 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); in sec_eng_init()
2009 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); in sec_eng_init()
2018 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); in sec_eng_init()
2021 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); in sec_eng_init()
2025 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); in sec_eng_init()
2028 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, in sec_eng_init()
2034 static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) in dmac_init() argument
2038 ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); in dmac_init()
2040 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); in dmac_init()
2044 ret = preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); in dmac_init()
2046 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); in dmac_init()
2050 ret = hfc_init(rtwdev, true, true, true); in dmac_init()
2052 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); in dmac_init()
2056 ret = sta_sch_init(rtwdev); in dmac_init()
2058 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); in dmac_init()
2062 ret = mpdu_proc_init(rtwdev); in dmac_init()
2064 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); in dmac_init()
2068 ret = sec_eng_init(rtwdev); in dmac_init()
2070 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); in dmac_init()
2077 static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx) in addr_cam_init() argument
2083 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in addr_cam_init()
2087 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx); in addr_cam_init()
2089 val = rtw89_read32(rtwdev, reg); in addr_cam_init()
2092 rtw89_write32(rtwdev, reg, val); in addr_cam_init()
2095 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); in addr_cam_init()
2097 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); in addr_cam_init()
2104 static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx) in scheduler_init() argument
2110 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in scheduler_init()
2114 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx); in scheduler_init()
2115 if (rtwdev->chip->chip_id == RTL8852C) in scheduler_init()
2116 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, in scheduler_init()
2119 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, in scheduler_init()
2122 if (rtwdev->chip->chip_id == RTL8852B || rtwdev->chip->chip_id == RTL8851B) { in scheduler_init()
2123 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx); in scheduler_init()
2124 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); in scheduler_init()
2127 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx); in scheduler_init()
2128 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); in scheduler_init()
2130 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx); in scheduler_init()
2131 if (rtwdev->chip->chip_id == RTL8852C) { in scheduler_init()
2132 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, in scheduler_init()
2135 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, in scheduler_init()
2138 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, in scheduler_init()
2145 int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, in rtw89_mac_typ_fltr_opt() argument
2164 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); in rtw89_mac_typ_fltr_opt()
2170 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx); in rtw89_mac_typ_fltr_opt()
2173 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx); in rtw89_mac_typ_fltr_opt()
2176 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx); in rtw89_mac_typ_fltr_opt()
2179 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); in rtw89_mac_typ_fltr_opt()
2182 rtw89_write32(rtwdev, reg, val); in rtw89_mac_typ_fltr_opt()
2187 static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx) in rx_fltr_init() argument
2192 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in rx_fltr_init()
2197 ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST, in rx_fltr_init()
2202 mac_ftlr = rtwdev->hal.rx_fltr; in rx_fltr_init()
2207 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx), in rx_fltr_init()
2209 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx), in rx_fltr_init()
2215 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) in _patch_dis_resp_chk() argument
2226 switch (rtwdev->chip->chip_id) { in _patch_dis_resp_chk()
2229 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); in _patch_dis_resp_chk()
2230 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; in _patch_dis_resp_chk()
2231 rtw89_write32(rtwdev, reg, val32); in _patch_dis_resp_chk()
2233 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); in _patch_dis_resp_chk()
2234 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; in _patch_dis_resp_chk()
2235 rtw89_write32(rtwdev, reg, val32); in _patch_dis_resp_chk()
2238 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); in _patch_dis_resp_chk()
2239 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; in _patch_dis_resp_chk()
2240 rtw89_write32(rtwdev, reg, val32); in _patch_dis_resp_chk()
2242 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); in _patch_dis_resp_chk()
2243 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; in _patch_dis_resp_chk()
2244 rtw89_write32(rtwdev, reg, val32); in _patch_dis_resp_chk()
2249 static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx) in cca_ctrl_init() argument
2254 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in cca_ctrl_init()
2258 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx); in cca_ctrl_init()
2259 val = rtw89_read32(rtwdev, reg); in cca_ctrl_init()
2274 rtw89_write32(rtwdev, reg, val); in cca_ctrl_init()
2276 _patch_dis_resp_chk(rtwdev, mac_idx); in cca_ctrl_init()
2281 static int nav_ctrl_init(struct rtw89_dev *rtwdev) in nav_ctrl_init() argument
2283 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | in nav_ctrl_init()
2286 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); in nav_ctrl_init()
2291 static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx) in spatial_reuse_init() argument
2296 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in spatial_reuse_init()
2299 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx); in spatial_reuse_init()
2300 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); in spatial_reuse_init()
2305 static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) in tmac_init() argument
2310 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in tmac_init()
2314 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx); in tmac_init()
2315 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); in tmac_init()
2317 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx); in tmac_init()
2318 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); in tmac_init()
2320 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx); in tmac_init()
2321 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); in tmac_init()
2322 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); in tmac_init()
2327 static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) in trxptcl_init() argument
2329 const struct rtw89_chip_info *chip = rtwdev->chip; in trxptcl_init()
2334 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in trxptcl_init()
2338 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); in trxptcl_init()
2339 val = rtw89_read32(rtwdev, reg); in trxptcl_init()
2343 switch (rtwdev->chip->chip_id) { in trxptcl_init()
2356 rtw89_write32(rtwdev, reg, val); in trxptcl_init()
2358 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx); in trxptcl_init()
2359 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); in trxptcl_init()
2361 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx); in trxptcl_init()
2362 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); in trxptcl_init()
2363 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx); in trxptcl_init()
2364 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); in trxptcl_init()
2369 static void rst_bacam(struct rtw89_dev *rtwdev) in rst_bacam() argument
2374 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, in rst_bacam()
2379 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); in rst_bacam()
2381 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); in rst_bacam()
2384 static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) in rmac_init() argument
2395 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in rmac_init()
2400 rst_bacam(rtwdev); in rmac_init()
2402 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx); in rmac_init()
2403 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); in rmac_init()
2405 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx); in rmac_init()
2406 val = rtw89_read16(rtwdev, reg); in rmac_init()
2411 rtw89_write16(rtwdev, reg, val); in rmac_init()
2413 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx); in rmac_init()
2414 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); in rmac_init()
2416 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx); in rmac_init()
2418 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; in rmac_init()
2420 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; in rmac_init()
2422 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; in rmac_init()
2425 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); in rmac_init()
2427 if (rtwdev->chip->chip_id == RTL8852A && in rmac_init()
2428 rtwdev->hal.cv == CHIP_CBV) { in rmac_init()
2429 rtw89_write16_mask(rtwdev, in rmac_init()
2430 rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx), in rmac_init()
2432 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx), in rmac_init()
2436 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx); in rmac_init()
2437 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); in rmac_init()
2442 static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx) in cmac_com_init() argument
2444 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; in cmac_com_init()
2448 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in cmac_com_init()
2452 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); in cmac_com_init()
2453 val = rtw89_read32(rtwdev, reg); in cmac_com_init()
2457 rtw89_write32(rtwdev, reg, val); in cmac_com_init()
2460 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx); in cmac_com_init()
2461 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); in cmac_com_init()
2467 static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) in is_qta_dbcc() argument
2471 cfg = get_dle_mem_cfg(rtwdev, mode); in is_qta_dbcc()
2473 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); in is_qta_dbcc()
2480 static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) in ptcl_init() argument
2485 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in ptcl_init()
2489 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { in ptcl_init()
2490 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx); in ptcl_init()
2491 val = rtw89_read32(rtwdev, reg); in ptcl_init()
2497 rtw89_write32(rtwdev, reg, val); in ptcl_init()
2499 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx); in ptcl_init()
2500 val = rtw89_read32(rtwdev, reg); in ptcl_init()
2503 rtw89_write32(rtwdev, reg, val); in ptcl_init()
2507 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, in ptcl_init()
2509 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, in ptcl_init()
2513 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, in ptcl_init()
2516 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, in ptcl_init()
2523 static int cmac_dma_init(struct rtw89_dev *rtwdev, u8 mac_idx) in cmac_dma_init() argument
2525 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; in cmac_dma_init()
2532 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in cmac_dma_init()
2536 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx); in cmac_dma_init()
2537 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); in cmac_dma_init()
2542 static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) in cmac_init() argument
2546 ret = scheduler_init(rtwdev, mac_idx); in cmac_init()
2548 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); in cmac_init()
2552 ret = addr_cam_init(rtwdev, mac_idx); in cmac_init()
2554 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, in cmac_init()
2559 ret = rx_fltr_init(rtwdev, mac_idx); in cmac_init()
2561 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, in cmac_init()
2566 ret = cca_ctrl_init(rtwdev, mac_idx); in cmac_init()
2568 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, in cmac_init()
2573 ret = nav_ctrl_init(rtwdev); in cmac_init()
2575 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, in cmac_init()
2580 ret = spatial_reuse_init(rtwdev, mac_idx); in cmac_init()
2582 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", in cmac_init()
2587 ret = tmac_init(rtwdev, mac_idx); in cmac_init()
2589 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); in cmac_init()
2593 ret = trxptcl_init(rtwdev, mac_idx); in cmac_init()
2595 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); in cmac_init()
2599 ret = rmac_init(rtwdev, mac_idx); in cmac_init()
2601 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); in cmac_init()
2605 ret = cmac_com_init(rtwdev, mac_idx); in cmac_init()
2607 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); in cmac_init()
2611 ret = ptcl_init(rtwdev, mac_idx); in cmac_init()
2613 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); in cmac_init()
2617 ret = cmac_dma_init(rtwdev, mac_idx); in cmac_init()
2619 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); in cmac_init()
2626 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, in rtw89_mac_read_phycap() argument
2635 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); in rtw89_mac_read_phycap()
2645 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) in rtw89_mac_setup_phycap() argument
2647 struct rtw89_efuse *efuse = &rtwdev->efuse; in rtw89_mac_setup_phycap()
2648 struct rtw89_hal *hal = &rtwdev->hal; in rtw89_mac_setup_phycap()
2649 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_mac_setup_phycap()
2658 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); in rtw89_mac_setup_phycap()
2689 rtw89_debug(rtwdev, RTW89_DBG_FW, in rtw89_mac_setup_phycap()
2693 rtw89_debug(rtwdev, RTW89_DBG_FW, in rtw89_mac_setup_phycap()
2696 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); in rtw89_mac_setup_phycap()
2697 rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity); in rtw89_mac_setup_phycap()
2702 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, in rtw89_hw_sch_tx_en_h2c() argument
2717 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); in rtw89_hw_sch_tx_en_h2c()
2727 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, in rtw89_set_hw_sch_tx_en() argument
2730 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx); in rtw89_set_hw_sch_tx_en()
2734 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in rtw89_set_hw_sch_tx_en()
2738 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) in rtw89_set_hw_sch_tx_en()
2739 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, in rtw89_set_hw_sch_tx_en()
2742 val = rtw89_read16(rtwdev, reg); in rtw89_set_hw_sch_tx_en()
2744 rtw89_write16(rtwdev, reg, val); in rtw89_set_hw_sch_tx_en()
2749 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, in rtw89_set_hw_sch_tx_en_v1() argument
2752 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx); in rtw89_set_hw_sch_tx_en_v1()
2756 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in rtw89_set_hw_sch_tx_en_v1()
2760 val = rtw89_read32(rtwdev, reg); in rtw89_set_hw_sch_tx_en_v1()
2762 rtw89_write32(rtwdev, reg, val); in rtw89_set_hw_sch_tx_en_v1()
2767 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, in rtw89_mac_stop_sch_tx() argument
2772 *tx_en = rtw89_read16(rtwdev, in rtw89_mac_stop_sch_tx()
2773 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx)); in rtw89_mac_stop_sch_tx()
2777 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, in rtw89_mac_stop_sch_tx()
2783 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, in rtw89_mac_stop_sch_tx()
2789 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, in rtw89_mac_stop_sch_tx()
2795 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, in rtw89_mac_stop_sch_tx()
2808 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, in rtw89_mac_stop_sch_tx_v1() argument
2813 *tx_en = rtw89_read32(rtwdev, in rtw89_mac_stop_sch_tx_v1()
2814 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx)); in rtw89_mac_stop_sch_tx_v1()
2818 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, in rtw89_mac_stop_sch_tx_v1()
2824 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, in rtw89_mac_stop_sch_tx_v1()
2830 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, in rtw89_mac_stop_sch_tx_v1()
2836 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, in rtw89_mac_stop_sch_tx_v1()
2849 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) in rtw89_mac_resume_sch_tx() argument
2853 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); in rtw89_mac_resume_sch_tx()
2861 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) in rtw89_mac_resume_sch_tx_v1() argument
2865 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, in rtw89_mac_resume_sch_tx_v1()
2874 int rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) in rtw89_mac_dle_buf_req() argument
2882 rtw89_write32(rtwdev, reg, val); in rtw89_mac_dle_buf_req()
2887 1, 2000, false, rtwdev, reg); in rtw89_mac_dle_buf_req()
2898 int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev, in rtw89_mac_set_cpuio() argument
2912 rtw89_write32(rtwdev, reg, val); in rtw89_mac_set_cpuio()
2924 rtw89_write32(rtwdev, reg, val); in rtw89_mac_set_cpuio()
2935 rtw89_write32(rtwdev, reg, val); in rtw89_mac_set_cpuio()
2940 1, 2000, false, rtwdev, reg); in rtw89_mac_set_cpuio()
2951 static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) in dle_quota_change() argument
2958 cfg = get_dle_mem_cfg(rtwdev, mode); in dle_quota_change()
2960 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); in dle_quota_change()
2965 dle_expected_used_size(rtwdev, mode)) { in dle_quota_change()
2966 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); in dle_quota_change()
2970 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); in dle_quota_change()
2972 ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, true, &pkt_id); in dle_quota_change()
2974 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); in dle_quota_change()
2984 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true); in dle_quota_change()
2986 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); in dle_quota_change()
2990 ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, false, &pkt_id); in dle_quota_change()
2992 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); in dle_quota_change()
3002 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false); in dle_quota_change()
3004 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); in dle_quota_change()
3011 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) in band_idle_ck_b() argument
3017 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in band_idle_ck_b()
3021 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx); in band_idle_ck_b()
3027 false, rtwdev, reg); in band_idle_ck_b()
3034 static int band1_enable(struct rtw89_dev *rtwdev) in band1_enable() argument
3041 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); in band1_enable()
3043 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); in band1_enable()
3048 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); in band1_enable()
3049 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); in band1_enable()
3050 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); in band1_enable()
3051 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); in band1_enable()
3054 ret = band_idle_ck_b(rtwdev, 0); in band1_enable()
3056 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); in band1_enable()
3060 ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode); in band1_enable()
3062 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); in band1_enable()
3067 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); in band1_enable()
3068 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); in band1_enable()
3071 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); in band1_enable()
3073 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); in band1_enable()
3077 ret = cmac_func_en(rtwdev, 1, true); in band1_enable()
3079 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); in band1_enable()
3083 ret = cmac_init(rtwdev, 1); in band1_enable()
3085 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); in band1_enable()
3089 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, in band1_enable()
3095 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) in rtw89_wdrls_imr_enable() argument
3097 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_wdrls_imr_enable()
3099 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); in rtw89_wdrls_imr_enable()
3100 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); in rtw89_wdrls_imr_enable()
3103 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) in rtw89_wsec_imr_enable() argument
3105 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_wsec_imr_enable()
3107 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); in rtw89_wsec_imr_enable()
3110 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) in rtw89_mpdu_trx_imr_enable() argument
3112 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; in rtw89_mpdu_trx_imr_enable()
3113 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_mpdu_trx_imr_enable()
3115 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, in rtw89_mpdu_trx_imr_enable()
3122 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, in rtw89_mpdu_trx_imr_enable()
3127 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, in rtw89_mpdu_trx_imr_enable()
3130 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, in rtw89_mpdu_trx_imr_enable()
3134 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, in rtw89_mpdu_trx_imr_enable()
3138 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) in rtw89_sta_sch_imr_enable() argument
3140 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_sta_sch_imr_enable()
3142 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, in rtw89_sta_sch_imr_enable()
3146 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, in rtw89_sta_sch_imr_enable()
3150 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) in rtw89_txpktctl_imr_enable() argument
3152 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_txpktctl_imr_enable()
3154 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, in rtw89_txpktctl_imr_enable()
3156 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, in rtw89_txpktctl_imr_enable()
3158 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, in rtw89_txpktctl_imr_enable()
3160 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, in rtw89_txpktctl_imr_enable()
3164 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) in rtw89_wde_imr_enable() argument
3166 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_wde_imr_enable()
3168 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); in rtw89_wde_imr_enable()
3169 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); in rtw89_wde_imr_enable()
3172 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) in rtw89_ple_imr_enable() argument
3174 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_ple_imr_enable()
3176 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); in rtw89_ple_imr_enable()
3177 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); in rtw89_ple_imr_enable()
3180 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) in rtw89_pktin_imr_enable() argument
3182 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, in rtw89_pktin_imr_enable()
3186 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) in rtw89_dispatcher_imr_enable() argument
3188 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_dispatcher_imr_enable()
3190 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, in rtw89_dispatcher_imr_enable()
3192 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, in rtw89_dispatcher_imr_enable()
3194 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, in rtw89_dispatcher_imr_enable()
3196 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, in rtw89_dispatcher_imr_enable()
3198 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, in rtw89_dispatcher_imr_enable()
3200 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, in rtw89_dispatcher_imr_enable()
3204 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) in rtw89_cpuio_imr_enable() argument
3206 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); in rtw89_cpuio_imr_enable()
3207 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); in rtw89_cpuio_imr_enable()
3210 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) in rtw89_bbrpt_imr_enable() argument
3212 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_bbrpt_imr_enable()
3214 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, in rtw89_bbrpt_imr_enable()
3216 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, in rtw89_bbrpt_imr_enable()
3218 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, in rtw89_bbrpt_imr_enable()
3220 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, in rtw89_bbrpt_imr_enable()
3222 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); in rtw89_bbrpt_imr_enable()
3225 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) in rtw89_scheduler_imr_enable() argument
3229 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx); in rtw89_scheduler_imr_enable()
3230 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | in rtw89_scheduler_imr_enable()
3232 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); in rtw89_scheduler_imr_enable()
3235 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) in rtw89_ptcl_imr_enable() argument
3237 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_ptcl_imr_enable()
3240 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx); in rtw89_ptcl_imr_enable()
3241 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); in rtw89_ptcl_imr_enable()
3242 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); in rtw89_ptcl_imr_enable()
3245 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) in rtw89_cdma_imr_enable() argument
3247 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_cdma_imr_enable()
3248 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; in rtw89_cdma_imr_enable()
3251 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx); in rtw89_cdma_imr_enable()
3252 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); in rtw89_cdma_imr_enable()
3253 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); in rtw89_cdma_imr_enable()
3256 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx); in rtw89_cdma_imr_enable()
3257 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); in rtw89_cdma_imr_enable()
3258 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); in rtw89_cdma_imr_enable()
3262 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) in rtw89_phy_intf_imr_enable() argument
3264 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_phy_intf_imr_enable()
3267 reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx); in rtw89_phy_intf_imr_enable()
3268 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); in rtw89_phy_intf_imr_enable()
3269 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); in rtw89_phy_intf_imr_enable()
3272 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) in rtw89_rmac_imr_enable() argument
3274 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_rmac_imr_enable()
3277 reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx); in rtw89_rmac_imr_enable()
3278 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); in rtw89_rmac_imr_enable()
3279 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); in rtw89_rmac_imr_enable()
3282 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) in rtw89_tmac_imr_enable() argument
3284 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; in rtw89_tmac_imr_enable()
3287 reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx); in rtw89_tmac_imr_enable()
3288 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); in rtw89_tmac_imr_enable()
3289 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); in rtw89_tmac_imr_enable()
3292 static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, in rtw89_mac_enable_imr() argument
3297 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); in rtw89_mac_enable_imr()
3299 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", in rtw89_mac_enable_imr()
3305 rtw89_wdrls_imr_enable(rtwdev); in rtw89_mac_enable_imr()
3306 rtw89_wsec_imr_enable(rtwdev); in rtw89_mac_enable_imr()
3307 rtw89_mpdu_trx_imr_enable(rtwdev); in rtw89_mac_enable_imr()
3308 rtw89_sta_sch_imr_enable(rtwdev); in rtw89_mac_enable_imr()
3309 rtw89_txpktctl_imr_enable(rtwdev); in rtw89_mac_enable_imr()
3310 rtw89_wde_imr_enable(rtwdev); in rtw89_mac_enable_imr()
3311 rtw89_ple_imr_enable(rtwdev); in rtw89_mac_enable_imr()
3312 rtw89_pktin_imr_enable(rtwdev); in rtw89_mac_enable_imr()
3313 rtw89_dispatcher_imr_enable(rtwdev); in rtw89_mac_enable_imr()
3314 rtw89_cpuio_imr_enable(rtwdev); in rtw89_mac_enable_imr()
3315 rtw89_bbrpt_imr_enable(rtwdev); in rtw89_mac_enable_imr()
3317 rtw89_scheduler_imr_enable(rtwdev, mac_idx); in rtw89_mac_enable_imr()
3318 rtw89_ptcl_imr_enable(rtwdev, mac_idx); in rtw89_mac_enable_imr()
3319 rtw89_cdma_imr_enable(rtwdev, mac_idx); in rtw89_mac_enable_imr()
3320 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); in rtw89_mac_enable_imr()
3321 rtw89_rmac_imr_enable(rtwdev, mac_idx); in rtw89_mac_enable_imr()
3322 rtw89_tmac_imr_enable(rtwdev, mac_idx); in rtw89_mac_enable_imr()
3330 static void rtw89_mac_err_imr_ctrl(struct rtw89_dev *rtwdev, bool en) in rtw89_mac_err_imr_ctrl() argument
3332 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; in rtw89_mac_err_imr_ctrl()
3334 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, in rtw89_mac_err_imr_ctrl()
3336 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, in rtw89_mac_err_imr_ctrl()
3338 if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta) in rtw89_mac_err_imr_ctrl()
3339 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, in rtw89_mac_err_imr_ctrl()
3343 static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable) in rtw89_mac_dbcc_enable() argument
3348 ret = band1_enable(rtwdev); in rtw89_mac_dbcc_enable()
3350 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); in rtw89_mac_dbcc_enable()
3354 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); in rtw89_mac_dbcc_enable()
3356 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); in rtw89_mac_dbcc_enable()
3360 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); in rtw89_mac_dbcc_enable()
3367 static int set_host_rpr(struct rtw89_dev *rtwdev) in set_host_rpr() argument
3369 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { in set_host_rpr()
3370 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, in set_host_rpr()
3372 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, in set_host_rpr()
3375 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, in set_host_rpr()
3377 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, in set_host_rpr()
3381 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); in set_host_rpr()
3382 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); in set_host_rpr()
3387 static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev) in rtw89_mac_trx_init() argument
3389 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; in rtw89_mac_trx_init()
3392 ret = dmac_init(rtwdev, 0); in rtw89_mac_trx_init()
3394 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); in rtw89_mac_trx_init()
3398 ret = cmac_init(rtwdev, 0); in rtw89_mac_trx_init()
3400 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); in rtw89_mac_trx_init()
3404 if (is_qta_dbcc(rtwdev, qta_mode)) { in rtw89_mac_trx_init()
3405 ret = rtw89_mac_dbcc_enable(rtwdev, true); in rtw89_mac_trx_init()
3407 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); in rtw89_mac_trx_init()
3412 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); in rtw89_mac_trx_init()
3414 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); in rtw89_mac_trx_init()
3418 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); in rtw89_mac_trx_init()
3420 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); in rtw89_mac_trx_init()
3424 rtw89_mac_err_imr_ctrl(rtwdev, true); in rtw89_mac_trx_init()
3426 ret = set_host_rpr(rtwdev); in rtw89_mac_trx_init()
3428 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); in rtw89_mac_trx_init()
3435 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) in rtw89_disable_fw_watchdog() argument
3437 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; in rtw89_disable_fw_watchdog()
3441 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); in rtw89_disable_fw_watchdog()
3442 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); in rtw89_disable_fw_watchdog()
3446 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, in rtw89_disable_fw_watchdog()
3449 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); in rtw89_disable_fw_watchdog()
3452 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); in rtw89_disable_fw_watchdog()
3455 void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev) in rtw89_mac_disable_cpu() argument
3457 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); in rtw89_mac_disable_cpu()
3459 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); in rtw89_mac_disable_cpu()
3460 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | in rtw89_mac_disable_cpu()
3462 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); in rtw89_mac_disable_cpu()
3464 rtw89_disable_fw_watchdog(rtwdev); in rtw89_mac_disable_cpu()
3466 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); in rtw89_mac_disable_cpu()
3467 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); in rtw89_mac_disable_cpu()
3470 int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw) in rtw89_mac_enable_cpu() argument
3475 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) in rtw89_mac_enable_cpu()
3478 rtw89_write32(rtwdev, R_AX_UDM1, 0); in rtw89_mac_enable_cpu()
3479 rtw89_write32(rtwdev, R_AX_UDM2, 0); in rtw89_mac_enable_cpu()
3480 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); in rtw89_mac_enable_cpu()
3481 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); in rtw89_mac_enable_cpu()
3482 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); in rtw89_mac_enable_cpu()
3483 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); in rtw89_mac_enable_cpu()
3485 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); in rtw89_mac_enable_cpu()
3487 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); in rtw89_mac_enable_cpu()
3495 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); in rtw89_mac_enable_cpu()
3497 if (rtwdev->chip->chip_id == RTL8852B) in rtw89_mac_enable_cpu()
3498 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, in rtw89_mac_enable_cpu()
3501 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, in rtw89_mac_enable_cpu()
3503 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); in rtw89_mac_enable_cpu()
3508 ret = rtw89_fw_check_rdy(rtwdev); in rtw89_mac_enable_cpu()
3516 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) in rtw89_mac_dmac_pre_init() argument
3518 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; in rtw89_mac_dmac_pre_init()
3528 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); in rtw89_mac_dmac_pre_init()
3534 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); in rtw89_mac_dmac_pre_init()
3539 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); in rtw89_mac_dmac_pre_init()
3543 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); in rtw89_mac_dmac_pre_init()
3545 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, in rtw89_mac_dmac_pre_init()
3550 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); in rtw89_mac_dmac_pre_init()
3551 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); in rtw89_mac_dmac_pre_init()
3554 ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); in rtw89_mac_dmac_pre_init()
3556 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); in rtw89_mac_dmac_pre_init()
3560 ret = hfc_init(rtwdev, true, false, true); in rtw89_mac_dmac_pre_init()
3562 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); in rtw89_mac_dmac_pre_init()
3569 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) in rtw89_mac_enable_bb_rf() argument
3571 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, in rtw89_mac_enable_bb_rf()
3573 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, in rtw89_mac_enable_bb_rf()
3576 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); in rtw89_mac_enable_bb_rf()
3582 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) in rtw89_mac_disable_bb_rf() argument
3584 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, in rtw89_mac_disable_bb_rf()
3586 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, in rtw89_mac_disable_bb_rf()
3589 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); in rtw89_mac_disable_bb_rf()
3595 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev) in rtw89_mac_partial_init() argument
3599 ret = rtw89_mac_power_switch(rtwdev, true); in rtw89_mac_partial_init()
3601 rtw89_mac_power_switch(rtwdev, false); in rtw89_mac_partial_init()
3602 ret = rtw89_mac_power_switch(rtwdev, true); in rtw89_mac_partial_init()
3607 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); in rtw89_mac_partial_init()
3609 ret = rtw89_mac_dmac_pre_init(rtwdev); in rtw89_mac_partial_init()
3613 if (rtwdev->hci.ops->mac_pre_init) { in rtw89_mac_partial_init()
3614 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); in rtw89_mac_partial_init()
3619 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL); in rtw89_mac_partial_init()
3626 int rtw89_mac_init(struct rtw89_dev *rtwdev) in rtw89_mac_init() argument
3630 ret = rtw89_mac_partial_init(rtwdev); in rtw89_mac_init()
3634 ret = rtw89_chip_enable_bb_rf(rtwdev); in rtw89_mac_init()
3638 ret = rtw89_mac_sys_init(rtwdev); in rtw89_mac_init()
3642 ret = rtw89_mac_trx_init(rtwdev); in rtw89_mac_init()
3646 if (rtwdev->hci.ops->mac_post_init) { in rtw89_mac_init()
3647 ret = rtwdev->hci.ops->mac_post_init(rtwdev); in rtw89_mac_init()
3652 rtw89_fw_send_all_early_h2c(rtwdev); in rtw89_mac_init()
3653 rtw89_fw_h2c_set_ofld_cfg(rtwdev); in rtw89_mac_init()
3657 rtw89_mac_power_switch(rtwdev, false); in rtw89_mac_init()
3662 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) in rtw89_mac_dmac_tbl_init() argument
3666 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) in rtw89_mac_dmac_tbl_init()
3670 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, in rtw89_mac_dmac_tbl_init()
3672 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); in rtw89_mac_dmac_tbl_init()
3676 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) in rtw89_mac_cmac_tbl_init() argument
3678 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) in rtw89_mac_cmac_tbl_init()
3681 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, in rtw89_mac_cmac_tbl_init()
3683 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); in rtw89_mac_cmac_tbl_init()
3684 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); in rtw89_mac_cmac_tbl_init()
3685 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); in rtw89_mac_cmac_tbl_init()
3686 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); in rtw89_mac_cmac_tbl_init()
3687 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); in rtw89_mac_cmac_tbl_init()
3688 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); in rtw89_mac_cmac_tbl_init()
3689 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); in rtw89_mac_cmac_tbl_init()
3690 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); in rtw89_mac_cmac_tbl_init()
3693 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) in rtw89_mac_set_macid_pause() argument
3702 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && in rtw89_mac_set_macid_pause()
3703 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) in rtw89_mac_set_macid_pause()
3706 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); in rtw89_mac_set_macid_pause()
3710 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); in rtw89_mac_set_macid_pause()
3742 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_func_sw() argument
3748 if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) in rtw89_mac_port_cfg_func_sw()
3751 rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); in rtw89_mac_port_cfg_func_sw()
3752 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); in rtw89_mac_port_cfg_func_sw()
3753 rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); in rtw89_mac_port_cfg_func_sw()
3754 rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); in rtw89_mac_port_cfg_func_sw()
3758 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | in rtw89_mac_port_cfg_func_sw()
3760 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); in rtw89_mac_port_cfg_func_sw()
3761 rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); in rtw89_mac_port_cfg_func_sw()
3764 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_tx_rpt() argument
3770 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); in rtw89_mac_port_cfg_tx_rpt()
3772 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); in rtw89_mac_port_cfg_tx_rpt()
3775 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_rx_rpt() argument
3781 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); in rtw89_mac_port_cfg_rx_rpt()
3783 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); in rtw89_mac_port_cfg_rx_rpt()
3786 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_net_type() argument
3791 rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, in rtw89_mac_port_cfg_net_type()
3795 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_bcn_prct() argument
3803 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); in rtw89_mac_port_cfg_bcn_prct()
3805 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); in rtw89_mac_port_cfg_bcn_prct()
3808 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_rx_sw() argument
3817 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); in rtw89_mac_port_cfg_rx_sw()
3819 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); in rtw89_mac_port_cfg_rx_sw()
3822 static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_rx_sync() argument
3830 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); in rtw89_mac_port_cfg_rx_sync()
3832 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); in rtw89_mac_port_cfg_rx_sync()
3835 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_tx_sw() argument
3843 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); in rtw89_mac_port_cfg_tx_sw()
3845 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); in rtw89_mac_port_cfg_tx_sw()
3848 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_bcn_intv() argument
3855 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, in rtw89_mac_port_cfg_bcn_intv()
3859 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_hiq_win() argument
3871 reg = rtw89_mac_reg_by_idx(rtwdev, hiq_win_addr[port], rtwvif->mac_idx); in rtw89_mac_port_cfg_hiq_win()
3872 rtw89_write8(rtwdev, reg, win); in rtw89_mac_port_cfg_hiq_win()
3875 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_hiq_dtim() argument
3882 addr = rtw89_mac_reg_by_idx(rtwdev, R_AX_MD_TSFT_STMP_CTL, rtwvif->mac_idx); in rtw89_mac_port_cfg_hiq_dtim()
3883 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); in rtw89_mac_port_cfg_hiq_dtim()
3885 rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, in rtw89_mac_port_cfg_hiq_dtim()
3889 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_bcn_setup_time() argument
3894 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, in rtw89_mac_port_cfg_bcn_setup_time()
3898 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_bcn_hold_time() argument
3903 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, in rtw89_mac_port_cfg_bcn_hold_time()
3907 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_bcn_mask_area() argument
3912 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, in rtw89_mac_port_cfg_bcn_mask_area()
3916 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_tbtt_early() argument
3921 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, in rtw89_mac_port_cfg_tbtt_early()
3925 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_bss_color() argument
3941 reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif->mac_idx); in rtw89_mac_port_cfg_bss_color()
3942 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); in rtw89_mac_port_cfg_bss_color()
3945 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_mbssid() argument
3955 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MBSSID_CTRL, rtwvif->mac_idx); in rtw89_mac_port_cfg_mbssid()
3956 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); in rtw89_mac_port_cfg_mbssid()
3960 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_hiq_drop() argument
3967 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MBSSID_DROP_0, rtwvif->mac_idx); in rtw89_mac_port_cfg_hiq_drop()
3968 val = rtw89_read32(rtwdev, reg); in rtw89_mac_port_cfg_hiq_drop()
3972 rtw89_write32(rtwdev, reg, val); in rtw89_mac_port_cfg_hiq_drop()
3975 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_func_en() argument
3981 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, in rtw89_mac_port_cfg_func_en()
3984 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, in rtw89_mac_port_cfg_func_en()
3988 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_bcn_early() argument
3993 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, in rtw89_mac_port_cfg_bcn_early()
3997 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, in rtw89_mac_port_cfg_tbtt_shift() argument
4003 if (rtwdev->chip->chip_id != RTL8852C) in rtw89_mac_port_cfg_tbtt_shift()
4013 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift, in rtw89_mac_port_cfg_tbtt_shift()
4017 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, in rtw89_mac_port_tsf_sync() argument
4025 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PORT0_TSF_SYNC + rtwvif->port * 4, in rtw89_mac_port_tsf_sync()
4028 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); in rtw89_mac_port_tsf_sync()
4029 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); in rtw89_mac_port_tsf_sync()
4030 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); in rtw89_mac_port_tsf_sync()
4033 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, in rtw89_mac_port_tsf_sync_rand() argument
4043 rtw89_mac_port_tsf_sync(rtwdev, rtwvif, rtwvif_src, in rtw89_mac_port_tsf_sync_rand()
4049 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) in rtw89_mac_port_tsf_resync_all() argument
4055 rtw89_for_each_rtwvif(rtwdev, tmp) { in rtw89_mac_port_tsf_resync_all()
4067 rtw89_for_each_rtwvif(rtwdev, tmp) in rtw89_mac_port_tsf_resync_all()
4068 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, &n_offset); in rtw89_mac_port_tsf_resync_all()
4071 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) in rtw89_mac_vif_init() argument
4075 ret = rtw89_mac_port_update(rtwdev, rtwvif); in rtw89_mac_vif_init()
4079 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); in rtw89_mac_vif_init()
4080 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); in rtw89_mac_vif_init()
4082 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false); in rtw89_mac_vif_init()
4086 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE); in rtw89_mac_vif_init()
4090 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true); in rtw89_mac_vif_init()
4094 ret = rtw89_cam_init(rtwdev, rtwvif); in rtw89_mac_vif_init()
4098 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); in rtw89_mac_vif_init()
4102 ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif); in rtw89_mac_vif_init()
4109 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) in rtw89_mac_vif_deinit() argument
4113 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE); in rtw89_mac_vif_deinit()
4117 rtw89_cam_deinit(rtwdev, rtwvif); in rtw89_mac_vif_deinit()
4119 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); in rtw89_mac_vif_deinit()
4126 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) in rtw89_mac_port_update() argument
4133 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); in rtw89_mac_port_update()
4134 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); in rtw89_mac_port_update()
4135 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); in rtw89_mac_port_update()
4136 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); in rtw89_mac_port_update()
4137 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); in rtw89_mac_port_update()
4138 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); in rtw89_mac_port_update()
4139 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif); in rtw89_mac_port_update()
4140 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif); in rtw89_mac_port_update()
4141 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); in rtw89_mac_port_update()
4142 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif); in rtw89_mac_port_update()
4143 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif); in rtw89_mac_port_update()
4144 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); in rtw89_mac_port_update()
4145 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); in rtw89_mac_port_update()
4146 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); in rtw89_mac_port_update()
4147 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); in rtw89_mac_port_update()
4148 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); in rtw89_mac_port_update()
4149 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif); in rtw89_mac_port_update()
4150 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); in rtw89_mac_port_update()
4151 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); in rtw89_mac_port_update()
4152 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, true); in rtw89_mac_port_update()
4153 rtw89_mac_port_tsf_resync_all(rtwdev); in rtw89_mac_port_update()
4155 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); in rtw89_mac_port_update()
4160 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, in rtw89_mac_port_get_tsf() argument
4167 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif->mac_idx, RTW89_CMAC_SEL); in rtw89_mac_port_get_tsf()
4171 tsf_low = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_l); in rtw89_mac_port_get_tsf()
4172 tsf_high = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_h); in rtw89_mac_port_get_tsf()
4197 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, in rtw89_mac_set_he_obss_narrow_bw_ru() argument
4201 struct ieee80211_hw *hw = rtwdev->hw; in rtw89_mac_set_he_obss_narrow_bw_ru()
4215 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, rtwvif->mac_idx); in rtw89_mac_set_he_obss_narrow_bw_ru()
4217 rtw89_write32_clr(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); in rtw89_mac_set_he_obss_narrow_bw_ru()
4219 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); in rtw89_mac_set_he_obss_narrow_bw_ru()
4222 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) in rtw89_mac_stop_ap() argument
4224 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, false); in rtw89_mac_stop_ap()
4227 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) in rtw89_mac_add_vif() argument
4231 rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, in rtw89_mac_add_vif()
4236 ret = rtw89_mac_vif_init(rtwdev, rtwvif); in rtw89_mac_add_vif()
4243 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); in rtw89_mac_add_vif()
4248 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) in rtw89_mac_remove_vif() argument
4252 ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); in rtw89_mac_remove_vif()
4253 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); in rtw89_mac_remove_vif()
4259 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) in rtw89_mac_c2h_macid_pause() argument
4263 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) in rtw89_is_op_chan() argument
4265 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; in rtw89_is_op_chan()
4271 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, in rtw89_mac_c2h_scanofld_rsp() argument
4274 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; in rtw89_mac_c2h_scanofld_rsp()
4278 u32 last_chan = rtwdev->scan_info.last_chan_idx; in rtw89_mac_c2h_scanofld_rsp()
4292 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) in rtw89_mac_c2h_scanofld_rsp()
4295 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, in rtw89_mac_c2h_scanofld_rsp()
4301 if (rtw89_is_op_chan(rtwdev, band, chan)) in rtw89_mac_c2h_scanofld_rsp()
4302 ieee80211_stop_queues(rtwdev->hw); in rtw89_mac_c2h_scanofld_rsp()
4307 ret = rtw89_hw_scan_offload(rtwdev, vif, true); in rtw89_mac_c2h_scanofld_rsp()
4309 rtw89_hw_scan_abort(rtwdev, vif); in rtw89_mac_c2h_scanofld_rsp()
4310 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); in rtw89_mac_c2h_scanofld_rsp()
4313 rtw89_hw_scan_complete(rtwdev, vif, false); in rtw89_mac_c2h_scanofld_rsp()
4317 if (rtw89_is_op_chan(rtwdev, band, chan)) { in rtw89_mac_c2h_scanofld_rsp()
4318 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, in rtw89_mac_c2h_scanofld_rsp()
4319 &rtwdev->scan_info.op_chan); in rtw89_mac_c2h_scanofld_rsp()
4320 ieee80211_wake_queues(rtwdev->hw); in rtw89_mac_c2h_scanofld_rsp()
4324 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, in rtw89_mac_c2h_scanofld_rsp()
4334 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, in rtw89_mac_bcn_fltr_rpt() argument
4352 rtw89_debug(rtwdev, RTW89_DBG_FW, in rtw89_mac_bcn_fltr_rpt()
4358 if (!rtwdev->scanning && !rtwvif->offchan) in rtw89_mac_bcn_fltr_rpt()
4361 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true); in rtw89_mac_bcn_fltr_rpt()
4382 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, in rtw89_mac_c2h_bcn_fltr_rpt() argument
4387 rtw89_for_each_rtwvif(rtwdev, rtwvif) in rtw89_mac_c2h_bcn_fltr_rpt()
4388 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif, c2h); in rtw89_mac_c2h_bcn_fltr_rpt()
4392 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) in rtw89_mac_c2h_rec_ack() argument
4396 rtw89_debug(rtwdev, RTW89_DBG_FW, in rtw89_mac_c2h_rec_ack()
4405 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) in rtw89_mac_c2h_done_ack() argument
4408 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; in rtw89_mac_c2h_done_ack()
4419 rtw89_debug(rtwdev, RTW89_DBG_FW, in rtw89_mac_c2h_done_ack()
4446 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) in rtw89_mac_c2h_log() argument
4448 rtw89_fw_log_dump(rtwdev, c2h->data, len); in rtw89_mac_c2h_log()
4452 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) in rtw89_mac_c2h_bcn_cnt() argument
4457 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, in rtw89_mac_c2h_pkt_ofld_rsp() argument
4460 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait; in rtw89_mac_c2h_pkt_ofld_rsp()
4469 rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n", in rtw89_mac_c2h_pkt_ofld_rsp()
4479 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, in rtw89_mac_c2h_tsf32_toggle_rpt() argument
4485 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) in rtw89_mac_c2h_mcc_rcv_ack() argument
4502 rtw89_debug(rtwdev, RTW89_DBG_CHAN, in rtw89_mac_c2h_mcc_rcv_ack()
4507 rtw89_debug(rtwdev, RTW89_DBG_CHAN, in rtw89_mac_c2h_mcc_rcv_ack()
4512 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) in rtw89_mac_c2h_mcc_req_ack() argument
4535 rtw89_debug(rtwdev, RTW89_DBG_CHAN, in rtw89_mac_c2h_mcc_req_ack()
4540 rtw89_debug(rtwdev, RTW89_DBG_CHAN, in rtw89_mac_c2h_mcc_req_ack()
4549 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); in rtw89_mac_c2h_mcc_req_ack()
4553 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) in rtw89_mac_c2h_mcc_tsf_rpt() argument
4568 rtw89_debug(rtwdev, RTW89_DBG_CHAN, in rtw89_mac_c2h_mcc_tsf_rpt()
4574 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); in rtw89_mac_c2h_mcc_tsf_rpt()
4578 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) in rtw89_mac_c2h_mcc_status_rpt() argument
4630 rtw89_debug(rtwdev, RTW89_DBG_CHAN, in rtw89_mac_c2h_mcc_status_rpt()
4635 rtw89_debug(rtwdev, RTW89_DBG_CHAN, in rtw89_mac_c2h_mcc_status_rpt()
4644 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); in rtw89_mac_c2h_mcc_status_rpt()
4648 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev,
4661 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev,
4670 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev,
4678 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func) in rtw89_mac_c2h_chk_atomic() argument
4703 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, in rtw89_mac_c2h_handle() argument
4706 void (*handler)(struct rtw89_dev *rtwdev, in rtw89_mac_c2h_handle()
4725 rtw89_info(rtwdev, "c2h class %d not support\n", class); in rtw89_mac_c2h_handle()
4729 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, in rtw89_mac_c2h_handle()
4733 handler(rtwdev, skb, len); in rtw89_mac_c2h_handle()
4736 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, in rtw89_mac_get_txpwr_cr() argument
4740 const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; in rtw89_mac_get_txpwr_cr()
4742 u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); in rtw89_mac_get_txpwr_cr()
4745 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", in rtw89_mac_get_txpwr_cr()
4752 rtw89_err(rtwdev, in rtw89_mac_get_txpwr_cr()
4762 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", in rtw89_mac_get_txpwr_cr()
4769 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) in rtw89_mac_cfg_ppdu_status() argument
4771 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx); in rtw89_mac_cfg_ppdu_status()
4774 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in rtw89_mac_cfg_ppdu_status()
4779 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); in rtw89_mac_cfg_ppdu_status()
4783 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | in rtw89_mac_cfg_ppdu_status()
4787 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, in rtw89_mac_cfg_ppdu_status()
4794 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) in rtw89_mac_update_rts_threshold() argument
4802 struct ieee80211_hw *hw = rtwdev->hw; in rtw89_mac_update_rts_threshold()
4818 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AGG_LEN_HT_0, mac_idx); in rtw89_mac_update_rts_threshold()
4819 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); in rtw89_mac_update_rts_threshold()
4820 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); in rtw89_mac_update_rts_threshold()
4823 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) in rtw89_mac_flush_txq() argument
4828 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) in rtw89_mac_flush_txq()
4832 10000, 200000, false, rtwdev); in rtw89_mac_flush_txq()
4833 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) in rtw89_mac_flush_txq()
4834 rtw89_info(rtwdev, "timed out to flush queues\n"); in rtw89_mac_flush_txq()
4837 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) in rtw89_mac_coex_init() argument
4844 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); in rtw89_mac_coex_init()
4845 if (rtwdev->chip->chip_id != RTL8851B) in rtw89_mac_coex_init()
4846 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); in rtw89_mac_coex_init()
4847 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); in rtw89_mac_coex_init()
4848 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); in rtw89_mac_coex_init()
4849 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); in rtw89_mac_coex_init()
4850 if (rtwdev->chip->chip_id != RTL8851B) in rtw89_mac_coex_init()
4851 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); in rtw89_mac_coex_init()
4853 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); in rtw89_mac_coex_init()
4855 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); in rtw89_mac_coex_init()
4857 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); in rtw89_mac_coex_init()
4859 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); in rtw89_mac_coex_init()
4863 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); in rtw89_mac_coex_init()
4865 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); in rtw89_mac_coex_init()
4871 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); in rtw89_mac_coex_init()
4874 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); in rtw89_mac_coex_init()
4876 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); in rtw89_mac_coex_init()
4877 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); in rtw89_mac_coex_init()
4879 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); in rtw89_mac_coex_init()
4882 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); in rtw89_mac_coex_init()
4885 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); in rtw89_mac_coex_init()
4888 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); in rtw89_mac_coex_init()
4890 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); in rtw89_mac_coex_init()
4898 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); in rtw89_mac_coex_init()
4900 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); in rtw89_mac_coex_init()
4908 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); in rtw89_mac_coex_init()
4910 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); in rtw89_mac_coex_init()
4913 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); in rtw89_mac_coex_init()
4915 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); in rtw89_mac_coex_init()
4918 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); in rtw89_mac_coex_init()
4920 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); in rtw89_mac_coex_init()
4930 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, in rtw89_mac_coex_init_v1() argument
4933 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, in rtw89_mac_coex_init_v1()
4935 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); in rtw89_mac_coex_init_v1()
4936 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); in rtw89_mac_coex_init_v1()
4937 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); in rtw89_mac_coex_init_v1()
4941 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, in rtw89_mac_coex_init_v1()
4943 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, in rtw89_mac_coex_init_v1()
4947 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, in rtw89_mac_coex_init_v1()
4958 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, in rtw89_mac_cfg_gnt() argument
4987 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); in rtw89_mac_cfg_gnt()
4989 rtw89_err(rtwdev, "Write LTE fail!\n"); in rtw89_mac_cfg_gnt()
4997 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, in rtw89_mac_cfg_gnt_v1() argument
5038 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); in rtw89_mac_cfg_gnt_v1()
5044 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) in rtw89_mac_cfg_plt() argument
5050 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); in rtw89_mac_cfg_plt()
5054 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band); in rtw89_mac_cfg_plt()
5064 rtw89_write16(rtwdev, reg, val); in rtw89_mac_cfg_plt()
5069 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) in rtw89_mac_cfg_sb() argument
5073 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); in rtw89_mac_cfg_sb()
5076 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) in rtw89_mac_cfg_sb()
5084 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); in rtw89_mac_cfg_sb()
5088 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) in rtw89_mac_get_sb() argument
5090 return rtw89_read32(rtwdev, R_AX_SCOREBOARD); in rtw89_mac_get_sb()
5093 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) in rtw89_mac_cfg_ctrl_path() argument
5095 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); in rtw89_mac_cfg_ctrl_path()
5098 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); in rtw89_mac_cfg_ctrl_path()
5104 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) in rtw89_mac_cfg_ctrl_path_v1() argument
5106 struct rtw89_btc *btc = &rtwdev->btc; in rtw89_mac_cfg_ctrl_path_v1()
5121 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); in rtw89_mac_cfg_ctrl_path_v1()
5125 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) in rtw89_mac_get_ctrl_path() argument
5127 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_mac_get_ctrl_path()
5133 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, in rtw89_mac_get_ctrl_path()
5139 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) in rtw89_mac_get_plt_cnt() argument
5144 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band); in rtw89_mac_get_plt_cnt()
5145 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); in rtw89_mac_get_plt_cnt()
5146 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); in rtw89_mac_get_plt_cnt()
5151 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, in rtw89_mac_bfee_standby_timer() argument
5156 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); in rtw89_mac_bfee_standby_timer()
5157 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); in rtw89_mac_bfee_standby_timer()
5159 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); in rtw89_mac_bfee_standby_timer()
5160 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, in rtw89_mac_bfee_standby_timer()
5163 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); in rtw89_mac_bfee_standby_timer()
5164 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, in rtw89_mac_bfee_standby_timer()
5169 static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) in rtw89_mac_bfee_ctrl() argument
5175 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); in rtw89_mac_bfee_ctrl()
5176 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); in rtw89_mac_bfee_ctrl()
5178 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); in rtw89_mac_bfee_ctrl()
5179 rtw89_write32_set(rtwdev, reg, mask); in rtw89_mac_bfee_ctrl()
5181 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); in rtw89_mac_bfee_ctrl()
5182 rtw89_write32_clr(rtwdev, reg, mask); in rtw89_mac_bfee_ctrl()
5186 static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx) in rtw89_mac_init_bfee() argument
5192 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in rtw89_mac_init_bfee()
5198 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx); in rtw89_mac_init_bfee()
5199 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); in rtw89_mac_init_bfee()
5201 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); in rtw89_mac_init_bfee()
5202 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); in rtw89_mac_init_bfee()
5204 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); in rtw89_mac_init_bfee()
5206 rtw89_write32(rtwdev, reg, val32); in rtw89_mac_init_bfee()
5207 rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); in rtw89_mac_init_bfee()
5208 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); in rtw89_mac_init_bfee()
5210 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); in rtw89_mac_init_bfee()
5211 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | in rtw89_mac_init_bfee()
5215 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); in rtw89_mac_init_bfee()
5216 rtw89_write32(rtwdev, reg, in rtw89_mac_init_bfee()
5221 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx); in rtw89_mac_init_bfee()
5222 rtw89_write32_set(rtwdev, reg, in rtw89_mac_init_bfee()
5228 static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev, in rtw89_mac_set_csi_para_reg() argument
5242 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in rtw89_mac_set_csi_para_reg()
5265 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); in rtw89_mac_set_csi_para_reg()
5266 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); in rtw89_mac_set_csi_para_reg()
5277 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); in rtw89_mac_set_csi_para_reg()
5279 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); in rtw89_mac_set_csi_para_reg()
5281 rtw89_write16(rtwdev, reg, val); in rtw89_mac_set_csi_para_reg()
5286 static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev, in rtw89_mac_csi_rrsc() argument
5296 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in rtw89_mac_csi_rrsc()
5315 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); in rtw89_mac_csi_rrsc()
5316 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); in rtw89_mac_csi_rrsc()
5317 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); in rtw89_mac_csi_rrsc()
5318 rtw89_write32(rtwdev, in rtw89_mac_csi_rrsc()
5319 rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), in rtw89_mac_csi_rrsc()
5325 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, in rtw89_mac_bf_assoc() argument
5331 rtw89_debug(rtwdev, RTW89_DBG_BF, in rtw89_mac_bf_assoc()
5333 rtw89_mac_init_bfee(rtwdev, rtwvif->mac_idx); in rtw89_mac_bf_assoc()
5334 rtw89_mac_set_csi_para_reg(rtwdev, vif, sta); in rtw89_mac_bf_assoc()
5335 rtw89_mac_csi_rrsc(rtwdev, vif, sta); in rtw89_mac_bf_assoc()
5339 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, in rtw89_mac_bf_disassoc() argument
5344 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); in rtw89_mac_bf_disassoc()
5347 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, in rtw89_mac_bf_set_gid_table() argument
5354 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); in rtw89_mac_bf_set_gid_table()
5357 rtw89_write32(rtwdev, in rtw89_mac_bf_set_gid_table()
5358 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx), in rtw89_mac_bf_set_gid_table()
5360 rtw89_write32(rtwdev, in rtw89_mac_bf_set_gid_table()
5361 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx), in rtw89_mac_bf_set_gid_table()
5365 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx), in rtw89_mac_bf_set_gid_table()
5367 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx), in rtw89_mac_bf_set_gid_table()
5369 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx), in rtw89_mac_bf_set_gid_table()
5371 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx), in rtw89_mac_bf_set_gid_table()
5376 struct rtw89_dev *rtwdev; member
5396 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, in rtw89_mac_bf_monitor_calc() argument
5401 data.rtwdev = rtwdev; in rtw89_mac_bf_monitor_calc()
5404 ieee80211_iterate_stations_atomic(rtwdev->hw, in rtw89_mac_bf_monitor_calc()
5408 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); in rtw89_mac_bf_monitor_calc()
5410 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); in rtw89_mac_bf_monitor_calc()
5412 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); in rtw89_mac_bf_monitor_calc()
5415 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) in _rtw89_mac_bf_monitor_track() argument
5417 struct rtw89_traffic_stats *stats = &rtwdev->stats; in _rtw89_mac_bf_monitor_track()
5420 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); in _rtw89_mac_bf_monitor_track()
5424 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); in _rtw89_mac_bf_monitor_track()
5430 rtw89_for_each_rtwvif(rtwdev, rtwvif) in _rtw89_mac_bf_monitor_track()
5431 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif->mac_idx, in _rtw89_mac_bf_monitor_track()
5438 rtw89_for_each_rtwvif(rtwdev, rtwvif) in _rtw89_mac_bf_monitor_track()
5439 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); in _rtw89_mac_bf_monitor_track()
5443 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, in __rtw89_mac_set_tx_time() argument
5454 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); in __rtw89_mac_set_tx_time()
5456 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in __rtw89_mac_set_tx_time()
5458 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); in __rtw89_mac_set_tx_time()
5462 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); in __rtw89_mac_set_tx_time()
5463 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, in __rtw89_mac_set_tx_time()
5470 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, in rtw89_mac_set_tx_time() argument
5477 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); in rtw89_mac_set_tx_time()
5479 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); in rtw89_mac_set_tx_time()
5486 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, in rtw89_mac_get_tx_time() argument
5496 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in rtw89_mac_get_tx_time()
5498 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); in rtw89_mac_get_tx_time()
5502 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); in rtw89_mac_get_tx_time()
5503 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; in rtw89_mac_get_tx_time()
5509 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, in rtw89_mac_set_tx_retry_limit() argument
5519 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); in rtw89_mac_set_tx_retry_limit()
5521 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); in rtw89_mac_set_tx_retry_limit()
5528 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, in rtw89_mac_get_tx_retry_limit() argument
5538 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in rtw89_mac_get_tx_retry_limit()
5540 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); in rtw89_mac_get_tx_retry_limit()
5544 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXCNT, mac_idx); in rtw89_mac_get_tx_retry_limit()
5545 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); in rtw89_mac_get_tx_retry_limit()
5551 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, in rtw89_mac_set_hw_muedca_ctrl() argument
5559 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); in rtw89_mac_set_hw_muedca_ctrl()
5563 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MUEDCA_EN, mac_idx); in rtw89_mac_set_hw_muedca_ctrl()
5565 rtw89_write16_set(rtwdev, reg, set); in rtw89_mac_set_hw_muedca_ctrl()
5567 rtw89_write16_clr(rtwdev, reg, set); in rtw89_mac_set_hw_muedca_ctrl()
5572 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) in rtw89_mac_write_xtal_si() argument
5582 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); in rtw89_mac_write_xtal_si()
5585 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); in rtw89_mac_write_xtal_si()
5587 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", in rtw89_mac_write_xtal_si()
5596 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) in rtw89_mac_read_xtal_si() argument
5606 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); in rtw89_mac_read_xtal_si()
5609 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); in rtw89_mac_read_xtal_si()
5611 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); in rtw89_mac_read_xtal_si()
5615 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); in rtw89_mac_read_xtal_si()
5622 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) in rtw89_mac_pkt_drop_sta() argument
5642 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); in rtw89_mac_pkt_drop_sta()
5650 struct rtw89_dev *rtwdev = rtwvif->rtwdev; in rtw89_mac_pkt_drop_vif_iter() local
5656 rtw89_mac_pkt_drop_sta(rtwdev, rtwsta); in rtw89_mac_pkt_drop_vif_iter()
5659 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) in rtw89_mac_pkt_drop_vif() argument
5661 ieee80211_iterate_stations_atomic(rtwdev->hw, in rtw89_mac_pkt_drop_vif()
5666 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, in rtw89_mac_ptk_drop_by_band_and_wait() argument
5678 50000, false, rtwdev); in rtw89_mac_ptk_drop_by_band_and_wait()
5679 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) in rtw89_mac_ptk_drop_by_band_and_wait()
5680 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); in rtw89_mac_ptk_drop_by_band_and_wait()