Lines Matching refs:rtw_write32_mask
156 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL, in rtw8723d_phy_set_param()
201 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); in rtw8723d_phy_set_param()
202 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20); in rtw8723d_phy_set_param()
413 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f); in rtw8723d_cfg_notch()
414 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); in rtw8723d_cfg_notch()
419 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); in rtw8723d_cfg_notch()
425 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb); in rtw8723d_cfg_notch()
426 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); in rtw8723d_cfg_notch()
431 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); in rtw8723d_cfg_notch()
434 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5); in rtw8723d_cfg_notch()
435 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); in rtw8723d_cfg_notch()
440 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); in rtw8723d_cfg_notch()
443 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); in rtw8723d_cfg_notch()
444 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); in rtw8723d_cfg_notch()
518 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0); in rtw8723d_set_channel_bb()
519 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0); in rtw8723d_set_channel_bb()
520 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 1); in rtw8723d_set_channel_bb()
521 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_MASK_RXBB_DFIR, 0xa); in rtw8723d_set_channel_bb()
524 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1); in rtw8723d_set_channel_bb()
525 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1); in rtw8723d_set_channel_bb()
526 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 0); in rtw8723d_set_channel_bb()
527 rtw_write32_mask(rtwdev, REG_CCK0_SYS, BIT_CCK_SIDE_BAND, in rtw8723d_set_channel_bb()
613 rtw_write32_mask(rtwdev, txagc->addr, txagc->mask, pwr_index); in rtw8723d_set_tx_power_index_by_rate()
649 rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 1); in rtw8723d_false_alarm_statistics()
650 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 1); in rtw8723d_false_alarm_statistics()
651 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KEEP, 1); in rtw8723d_false_alarm_statistics()
652 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KEEP, 1); in rtw8723d_false_alarm_statistics()
690 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 1); in rtw8723d_false_alarm_statistics()
691 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 0); in rtw8723d_false_alarm_statistics()
692 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 1); in rtw8723d_false_alarm_statistics()
693 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 0); in rtw8723d_false_alarm_statistics()
694 rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 0); in rtw8723d_false_alarm_statistics()
695 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 0); in rtw8723d_false_alarm_statistics()
696 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 0); in rtw8723d_false_alarm_statistics()
697 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 2); in rtw8723d_false_alarm_statistics()
698 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 0); in rtw8723d_false_alarm_statistics()
699 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 2); in rtw8723d_false_alarm_statistics()
700 rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 1); in rtw8723d_false_alarm_statistics()
701 rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 0); in rtw8723d_false_alarm_statistics()
775 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); in rtw8723d_iqk_restore_regs()
776 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, backup->igia); in rtw8723d_iqk_restore_regs()
778 rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, 0x50); in rtw8723d_iqk_restore_regs()
779 rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, backup->igib); in rtw8723d_iqk_restore_regs()
795 rtw_write32_mask(rtwdev, REG_PAD_CTRL1, BIT_BT_BTG_SEL, 0x1); in rtw8723d_iqk_config_path_ctrl()
823 rtw_write32_mask(rtwdev, REG_LTECOEX_PATH_CONTROL, BIT_LTE_MUX_CTRL_PATH, 0x1); in rtw8723d_iqk_config_lte_path_gnt()
939 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); in rtw8723d_iqk_one_shot()
968 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); in rtw8723d_iqk_txrx_path_post()
987 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); in rtw8723d_iqk_tx_path()
1048 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); in rtw8723d_iqk_rx_path()
1118 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); in rtw8723d_iqk_rx_path()
1158 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, in rtw8723d_iqk_fill_s1_matrix()
1160 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, in rtw8723d_iqk_fill_s1_matrix()
1165 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, in rtw8723d_iqk_fill_s1_matrix()
1167 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, in rtw8723d_iqk_fill_s1_matrix()
1169 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, in rtw8723d_iqk_fill_s1_matrix()
1181 rtw_write32_mask(rtwdev, REG_A_RXIQI, BIT_MASK_RXIQ_S1_X, in rtw8723d_iqk_fill_s1_matrix()
1183 rtw_write32_mask(rtwdev, REG_A_RXIQI, BIT_MASK_RXIQ_S1_Y1, in rtw8723d_iqk_fill_s1_matrix()
1185 rtw_write32_mask(rtwdev, REG_RXIQK_MATRIX_LSB_11N, BIT_MASK_RXIQ_S1_Y2, in rtw8723d_iqk_fill_s1_matrix()
1205 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, tx0_a); in rtw8723d_iqk_fill_s0_matrix()
1206 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, tx0_a_ext); in rtw8723d_iqk_fill_s0_matrix()
1211 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, tx0_c); in rtw8723d_iqk_fill_s0_matrix()
1212 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, tx0_c_ext); in rtw8723d_iqk_fill_s0_matrix()
1217 rtw_write32_mask(rtwdev, REG_RXIQ_AB_S0, BIT_MASK_RXIQ_X_S0, in rtw8723d_iqk_fill_s0_matrix()
1219 rtw_write32_mask(rtwdev, REG_RXIQ_AB_S0, BIT_MASK_RXIQ_Y_S0, in rtw8723d_iqk_fill_s0_matrix()
1242 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); in rtw8723d_iqk_rf_standby()
1245 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); in rtw8723d_iqk_rf_standby()
1314 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); in rtw8723d_iqk_precfg_path()
1336 rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf); in rtw8723d_iqk_one_round()
1419 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); in rtw8723d_iqk_one_round()
1543 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]); in rtw8723d_phy_cck_pd_set()
1544 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000, in rtw8723d_phy_cck_pd_set()
1746 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, in rtw8723d_set_iqk_matrix_by_result()
1756 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0, ele_D); in rtw8723d_set_iqk_matrix_by_result()
1757 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, ele_C); in rtw8723d_set_iqk_matrix_by_result()
1758 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, ele_A); in rtw8723d_set_iqk_matrix_by_result()
1760 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_EXT_S0, in rtw8723d_set_iqk_matrix_by_result()
1762 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, in rtw8723d_set_iqk_matrix_by_result()
1764 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, in rtw8723d_set_iqk_matrix_by_result()
1793 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, in rtw8723d_set_iqk_matrix()
1802 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, in rtw8723d_set_iqk_matrix()
1804 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_B_S0, in rtw8723d_set_iqk_matrix()
1806 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, in rtw8723d_set_iqk_matrix()
1808 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0, in rtw8723d_set_iqk_matrix()
1810 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_EXT_S0, 0x0); in rtw8723d_set_iqk_matrix()
1811 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, 0x0); in rtw8723d_set_iqk_matrix()
1812 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, 0x0); in rtw8723d_set_iqk_matrix()
1835 rtw_write32_mask(rtwdev, 0xab4, 0x000007FF, in rtw8723d_pwrtrack_set_cck_pwr()
1892 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL, in rtw8723d_pwrtrack_set_xtal()